Ternary logic circuit

Patent metadata

Field	Value
Publication number	US-11923846-B2
Application number	US-202217673772-A
Country	US
Kind code	B2
Filing date	Feb 16, 2022
Priority date	Jun 22, 2021
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

First claim

What is claimed is:

1. A ternary logic circuit comprising:
a first inverter unit electrically connected to an input terminal and an output terminal;
a second inverter unit electrically connected to the input terminal and the output terminal and arranged in parallel with the first inverter unit;
a first junction unit arranged between the first inverter unit and the output terminal and including a tunnel PN junction; and
a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction,
wherein, the first inverter unit includes a first transistor having a first threshold voltage and a second transistor that is arranged in series with the first transistor and has a second threshold voltage,
the second inverter unit includes a third transistor having a third threshold voltage and a fourth transistor that is arranged in series with the third transistor and has a fourth threshold voltage,
the first transistor and the third transistor include a p-type channel, and the second transistor and the fourth transistor include an n-type channel, and
when an absolute value of an input voltage applied to the input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

2. The ternary logic circuit of claim 1 , wherein an absolute value of the first threshold voltage is equal to an absolute value of the fourth threshold voltage, and
an absolute value of the second threshold voltage is equal to an absolute value of the third threshold voltage.

3. The ternary logic circuit of claim 1 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor comprise carbon nanotube transistors.

4. The ternary logic circuit of claim 3 , wherein the first transistor and the fourth transistor comprise carbon nanotubes having a first diameter,
the second transistor and the third transistor comprise carbon nanotubes having a second diameter, and
the first diameter is less than the second diameter.

5. The ternary logic circuit of claim 1 , wherein the first junction unit and the second junction unit include a carbon nanotube tunnel PN junction.

6. The ternary logic circuit of claim 5 , wherein an electric field applied to the carbon nanotube tunnel PN junction is equal to or greater than 1 MV/cm.

7. The ternary logic circuit of claim 5 , wherein the carbon nanotube tunnel PN junction has a first region that is highly doped with an n-type dopant and a second region that is highly doped with a p-type dopant.

8. The ternary logic circuit of claim 7 , wherein the carbon nanotube tunnel PN junction is doped at at least 3×10 18 cm −3 .

9. The ternary logic circuit of claim 5 , wherein, when the absolute value of the input voltage is greater than an absolute value of the first input voltage and less than an absolute value of the second input voltage, the carbon nanotube tunnel PN junction distributes a voltage by using a tunneling current.

10. The ternary logic circuit of claim 1 , wherein the first output voltage has a same magnitude as an operation voltage V DD , and
the second output voltage has half the magnitude as the operation voltage V DD /2, and
the third output voltage has the same magnitude as a ground voltage.

Assignees

• Ulsan Nat Inst Science & Tech Unist

Inventors

• Kim Kyung Rok
• Jeong Jae Won
• Choi Youngeun
• Kim Wooseok
• Jun Jae Hyeon

Classifications

• H03K19/08 Primary

  using semiconductor devices (H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12) · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/0948

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• G06F7/49

  Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix {non-linear PCM (G06F7/4824 takes precedence)} · CPC title