Systems and methods for liquid presentation detection

Patent metadata

Field	Value
Publication number	US-11923675-B2
Application number	US-202117644888-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Dec 17, 2021
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A data interconnect system includes: a plurality of pins arranged within a receptacle, a first one of the pins being a power pin, wherein the pins are electrically isolated from each other within the receptacle; a first switching network including a first plurality of parallel switching devices, each of the parallel switching devices of the first plurality of parallel switching devices coupling a respective one of the pins to a node; a first current path from the node to ground, the first current path including a current device; and a second current path, parallel to the first current path, the second current path including a resistor coupling the node to ground.

First claim

What is claimed is:

1. A data interconnect system comprising:
a plurality of pins arranged within a receptacle, a first one of the pins being a power pin, wherein the pins are electrically isolated from each other within the receptacle;
a first switching network including a first plurality of parallel switching devices, each of the parallel switching devices of the first plurality of parallel switching devices coupling a respective one of the pins to a node;
a first current path from the node to ground, the first current path including a current device; and
a second current path, parallel to the first current path, the second current path including a resistor coupling the node to ground.

2. The data interconnect system of claim 1 , further comprising an analog to digital converter coupled to the resistor.

3. The data interconnect system of claim 1 , further comprising a comparator having a first input coupled to the node and a second input coupled to a reference voltage.

4. The data interconnect system of claim 1 , further comprising a voltage detector coupled to the node.

5. The data interconnect system of claim 1 , wherein the current device included in the first current path comprises a current source.

6. The data interconnect system of claim 1 , wherein the current device included in the first current path comprises a variable resistor.

7. The data interconnect system of claim 1 , further comprising an integrated circuit device configured to operate the parallel switching devices to create closed circuits between the plurality of pins and the node.

8. The data interconnect system of claim 1 , wherein the current device includes:
a current source coupled to ground;
a variable resistor coupled to ground;
a second switching network coupling the current source and the variable resistor to the node.

9. The data interconnect system of claim 8 , further comprising control circuitry coupled to the second switching network, the control circuitry configured to operate the second switching network by creating closed circuits between the current source and the variable resistor.

10. A data interconnect system comprising:
a plurality of pins arranged within a receptacle, wherein the pins are electrically isolated from each other in the receptacle;
a first switching network including a first plurality of parallel switching devices, each of the parallel switching devices of the first plurality of parallel switching devices coupling a respective one of the pins to a first node;
a current device coupled to the first node;
a second switching network including a second plurality of parallel switching devices, each of the parallel switching devices of the second plurality of parallel switching devices coupling a respective one of the pins to a second node, wherein the second node is coupled to ground;
a power source coupled to the first node; and
a resistor coupling the first node to ground.

11. The data interconnect system of claim 10 , further comprising an analog to digital converter coupled to the resistor.

12. The data interconnect system of claim 10 , further comprising a comparator having a first input coupled to the first node and a second input coupled to a reference voltage.

13. The data interconnect system of claim 10 , further comprising a voltage detector coupled to the first node.

14. The data interconnect system of claim 10 , wherein the current device included comprises a current source.

15. The data interconnect system of claim 10 , wherein the current device comprises a variable resistor.

16. The data interconnect system of claim 10 , further comprising an integrated circuit device configured to operate the first plurality of parallel switching devices to create closed circuits between the plurality of pins and the first node.

17. The data interconnect system of claim 10 , further comprising an integrated circuit device configured to operate the second plurality of parallel switching devices to create closed circuits between the plurality of pins and the second node.

18. The data interconnect system of claim 10 , wherein the current device includes:
a current source coupled to ground;
a variable resistor coupled to ground;
a third switching network coupling the current source and the variable resistor to the first node.

19. The data interconnect system of claim 18 , further comprising an integrated circuit device configured to operate the third switching network by creating closed circuits between the current source and the variable resistor.

20. A method comprising:
controlling a switching network, including causing the switching network to open and close a plurality of parallel switching devices, wherein each parallel switching device of the plurality of parallel switching devices is coupled to a respective pin of a data interconnect receptacle, further wherein controlling the switching network includes:
closing a first switching device of the plurality of parallel switching devices, including creating a first conductive path between a first pin of the data interconnect receptacle and a voltage measuring device; and
closing a second switching device of the plurality of parallel switching devices, including creating a second conductive path between a second pin of the data interconnect receptacle and the voltage measuring device;
determining a presence of liquid between the first pin and a power source based on measuring a voltage created by closing the first switching device; and
performing an action in response to determining the presence of liquid.

21. The method of claim 20 , further comprising:
determining presence of liquid between the second pin and the power source based on measuring a voltage created by closing the second switching device.

22. The method of claim 20 , wherein performing the action includes displaying a warning on a user interface device of a wireless device that includes the data interconnect receptacle.

23. The method of claim 20 , wherein performing the action includes putting the data interconnect receptacle into a sink mode.

24. The method of claim 20 , wherein performing the action includes reducing a voltage level of the first pin or another pin within the data interconnect receptacle.

25. The method of claim 20 , further comprising:
repeating closing the first switching device and closing the second switching device according to a periodic interval.

26. A method comprising:
controlling a first switching network, including causing the first switching network to open and close a first plurality of parallel switching devices, wherein each parallel switching device of the first plurality of parallel switching devices is coupled to a respective pin of a data interconnect receptacle, further wherein controlling the first switching network includes:
closing a first switching device of the first plurality of parallel switching devices, including creating a first conductive path between a first pin of the data interconnect receptacle and a voltage measuring device; and
controlling a second switching network, including causing the second switching network to open and close a second plurality of parallel switching devices, further wherein controlling the second switching network includes:
closing a second switching device of the second plurality of parallel switching devices, including extending the first conductive path through a second pi

Assignees

• Qualcomm Inc

Inventors

• Guo Guoyong
• Kun Cheong

Classifications

• H02H5/00 Primary

  Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection (using simulators of the apparatus being protected H02H6/00; specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems H02H7/00) · CPC title

• H02H1/0007

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title