Computing device, a system and a method for parallel processing of data streams

US11922293B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11922293-B2
Application numberUS-201916571416-A
CountryUS
Kind codeB2
Filing dateSep 16, 2019
Priority dateOct 26, 2005
Publication dateMar 5, 2024
Grant dateMar 5, 2024

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  5. First independent claim

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Abstract

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An apparatus for identification of an input data against one or more learned signals is provided. The apparatus comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recognition of a previously learned signal, the apparatus being further configured to process the produced outputs from the number of computational cores and determining an identification of the input data based the produced outputs.

First claim

Opening claim text (preview).

We claim: 1. An apparatus for processing a data stream, comprising: a processing unit comprising a plurality of computational cores, wherein each computational core is configured to receive an input data stream and provide a unique output data stream, wherein each computational core of the plurality of computational cores comprises a liquid section; wherein liquid sections of the plurality of computational cores comprises leaky-to-threshold units (LTUs) and coupling node units (CNUs) that are used for connecting LTUs; wherein weightings and decay times of the CNUs of the plurality of computational cores are randomly set to randomly connect the LTUs of the plurality of computational cores, wherein at least two of the plurality of computational cores operate in parallel; an input interface configured to receive the input data stream and simultaneously provide the same received input data stream to each of the at least two of the plurality of computational cores; and an output interface configured to simultaneously receive the output data from each of the at least two of the plurality of computational cores. 2. The apparatus of claim 1 , further comprising: at least one register configured to be updated responsive of the output data. 3. The apparatus of claim 2 , wherein the at least one register contains at least one of: a mode of operation of the plurality of the computation cores, the input data, the output data, and an outcome indication based on the output data. 4. The apparatus of claim 3 , wherein the outcome indication is at least one of: winner-takes-all, majority voting, and statistical analysis. 5. The apparatus of claim 3 , wherein the outcome indication is provided based on a determination whether the plurality of computational cores identified the input data. 6. The apparatus of claim 1 , wherein the input data comprises temporal data. 7. The apparatus of claim 6 , wherein the temporal data comprises at least a segment of binary streaming data. 8. The apparatus of claim 1 , wherein the apparatus is configured to be asynchronously adaptive with respect to the input data. 9. The apparatus of claim 1 , wherein the apparatus is configured to perform based on the input data a task including at least one of: filtering unknown data streams, image recognition, speech recognition, clustering, indexing, routing, video signals analysis, video indexing, categorization, string matching, recognition tasks, verification tasks, tagging, and outlier detection. 10. The apparatus of claim 1 , wherein the input data stream comprises at least one of: signals, streams of signals, string, regular expression, sensor output signals, database records, processor outputs, naturally structured signals, speech signals, image signals, physiological signals, medical signals, and text signals. 11. The apparatus of claim 1 , wherein all of the plurality of computational cores are arranged to operate in parallel. 12. The apparatus of claim 1 , wherein the CNUs of the plurality of computational cores are randomly applied over a statistical distribution. 13. The apparatus of claim 12 , wherein the statistical distribution is a Gaussian distribution. 14. The apparatus of claim 1 , wherein the plurality of computational cores is divided to a plurality of subgroups of computational cores, wherein each of the subgroups of computational cores is configured for mapping variants of the input data stream. 15. The apparatus of claim 1 , wherein the processing unit is configured to capture at least one intrinsic dimension of the input data stream. 16. The apparatus of claim 1 wherein the connectivity of each computational core is unchanged. 17. The apparatus of claim 1 wherein when fed with the same input data stream different computational cores are arranged to output unique output data streams that differ from each other. 18. The apparatus of claim 1 wherein each computational core is adapted to provide the unique output data stream only based on the connectivity of the computational core without accessing a storage device. 19. A method for processing a data stream, comprising: randomly determining weightings and decay times of coupling node units (CNUs) that are used for randomly connecting leaky-to-threshold units (LTUs) of the liquid sections of the plurality of computational cores; configuring at least two of the plurality of computational cores to operate in parallel; receiving a data stream; simultaneously providing the data stream to each of the inputs of the at least two computational cores; and providing by each computational core of the at least two computational cores, a unique output data stream based on the data stream. 20. The method of claim 19 , wherein the CNUs of the plurality of computational cores are randomly applied over a statistical distribution. 21. The method of claim 20 , wherein the statistical distribution is a Gaussian distribution.

Assignees

Inventors

Classifications

  • G06N3/063Primary

    using electronic means · CPC title

  • Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title

  • Special purpose registers · CPC title

  • using a plurality of independent parallel functional units · CPC title

  • with adaptable data path · CPC title

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What does patent US11922293B2 cover?
An apparatus for identification of an input data against one or more learned signals is provided. The apparatus comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recog…
Who is the assignee on this patent?
Cortica Ltd
What technology area does this patent fall under?
Primary CPC classification G06N3/063. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 05 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).