Unit element for asynchronous analog multiplier accumulator

Patent metadata

Field	Value
Publication number	US-11922240-B2
Application number	US-202017139226-A
Country	US
Kind code	B2
Filing date	Dec 31, 2020
Priority date	Dec 31, 2020
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

First claim

We claim:

1. A unit element having a digital A input and a digital B input, the unit element comprising:
a plurality of AND-groups, each AND-group comprising a plurality of AND gates, each AND gate of each AND-group having one input coupled to a unique digital bit of the A input and the other AND gate inputs commonly coupled to a digital bit of the B input;
a plurality of analog charge lines, each analog charge line coupled to a respective output of an AND gate of each AND-group through a charge transfer capacitor of value C;
a charge summing unit comprising a plurality of charge summing capacitors, one terminal of each charge summing capacitor coupled to a respective analog charge line, the other terminals of the charge summing capacitors coupled to an input of an analog to digital converter;
each charge summing capacitor of the charge summing unit having a value Cs*2 n where n is the order of the respective analog charge line and a value Cs is smaller than the value C;
and where the largest value of Cs is smaller than ⅛th of an accumulated capacitance of charge transfer capacitors associated with AND gates coupled to an associated analog charge line.

2. The unit element of claim 1 where each analog charge line includes a gain balancing capacitor of sufficient value to equalize the capacitance applied to each analog charge line by a capacitance of the charge transfer capacitor.

3. The unit element of claim 2 where the gain balancing capacitor for each analog charge line is coupled between an associated analog charge line and ground.

4. The unit element of claim 2 where the gain balancing capacitor for each analog charge line is included in the value of Cs associated with each analog charge line.

5. The unit element of claim 1 where Cs is smaller than the value C by at least a factor of 16, 32, 64, or 128.

6. The unit element of claim 1 where the number of bits of at least one of the digital A input or the digital B input is between three and 5 bits.

7. The unit element of claim 1 where a different particular digital A or B bit is commonly applied to each AND gate of a product generator.

8. A multiplier-accumulator comprising:
an analog charge bus comprising a plurality of analog charge lines;
a plurality of unit elements, each unit element accepting a digital A input and a digital B input;
each said unit element comprising:
a plurality of product generators, each product generator comprising a plurality of AND gates, each AND gate of each product generator having one input coupled to a unique one of the bits of the digital A input and the other AND gate inputs commonly coupled to one of the bits of the B digital input, an output of each AND gate of each product generator coupled to a particular analog charge line through a charge transfer capacitor of value C;

a charge summing block comprising a plurality of charge scaling capacitors, each charge scaling capacitor having one terminal coupled to a respective analog charge line and the other terminal connected to an input of an analog to digital converter generating a multiplication result;
each charge scaling capacitor having a value Cs*2 n where n is the order of the respective analog charge line;
and where the charge transfer capacitor value is at least 10 times greater than the largest charge scaling capacitor.

9. The multiplier-accumulator of claim 8 where the number of AND gates of each product generator is between three and five.

10. The multiplier-accumulator of claim 8 where the charge transfer capacitors and charge scaling capacitors are reset prior to a multiply-accumulate operation.

11. The multiplier-accumulator of claim 8 where a bias charge is applied to at least one analog charge line.

12. A dot product generator comprising:
an analog charge bus comprising a plurality of analog charge lines;
a plurality of unit elements, each unit element having an A digital input and a B digital input, each unit element comprising:
a plurality of AND-groups, each AND-group comprising a plurality of AND gates, one for each digital bit of A or B inputs, each AND gate of an AND-group having one input coupled to each of the A digital input bits and the other input coupled to a unique one of the B digital input bits, an output of each AND gate of each AND-group coupled to an analog charge line through a charge transfer capacitor;
a charge summing unit comprising a plurality of binary-weighted charge summing capacitors, each charge summing capacitor having a first terminal coupled to a unique analog charge line, the charge summing capacitors having a second terminal connected together and to an input of an analog to digital converter
and where the largest value of a charge summing capacitor is smaller than ⅛th of an accumulated capacitance of charge transfer capacitors associated with AND gates coupled to an associated analog charge line.

13. The dot product generator of claim 12 where the plurality of binary weighted charge summing capacitors are selected to generate a binary weighting of each analog charge line.

14. The dot product generator of claim 12 where gain balancing capacitors are coupled to each analog charge line to equalize the capacitance contributed by each charge transfer capacitor to an associated analog charge line.

15. The dot product generator of claim 14 where the gain balancing capacitors have one terminal connected to an associated analog charge line and the other terminal is connected to either a ground reference or incorporated into a capacitance of the associated charge summing capacitor.

16. The dot product generator of claim 14 where a bias is applied to the analog charge bus.

17. The dot product generator of claim 16 where the bias is a plurality of bias capacitors having one terminal coupled to a unique analog charge line and the other terminal connected to a digital bias input bit.

18. The dot product generator of claim 14 where each charge transfer capacitor and each charge summing capacitor is discharged prior to an application of an A input value and/or a B input value.

Assignees

• Ceremorphic Inc

Inventors

• Boesch Ryan
• Kraemer Martin
• Xiong Wei

Classifications

• G06G7/16 Primary

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06J1/00

  Hybrid computing arrangements · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G06G7/184

  using capacitive elements · CPC title