Configurable reduced memory startup

Patent metadata

Field	Value
Publication number	US-11922172-B2
Application number	US-202017028315-A
Country	US
Kind code	B2
Filing date	Sep 22, 2020
Priority date	Aug 6, 2020
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.

First claim

We claim:

1. A computing system comprising:
a network controller;
a processor coupled to the network controller; and
a memory module coupled to the processor, the memory module including set of instructions, which when executed by the processor, cause the processor to:
enable, during a boot sequence, a first set of ranks in the memory module based on a battery status and a user interface,
disable, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface,
generate a map between a system address space and a first set of banks in the first set of ranks, and
exclude a second set of banks in the first set of ranks from the map.

2. The computing system of claim 1 , further including a memory controller, wherein when executed by the memory controller, the instructions cause the memory controller to:
monitor a write activity with respect to the first set of banks, and
disable refreshes in one or banks in the first set of banks based on the write activity.

3. The computing system of claim 1 , wherein the user interface is to include a configuration object structure that defines one or more of memory properties, a memory configuration, a performance configuration, a user interface elements configuration, a storage configuration or a hot swap configuration.

4. The computing system of claim 1 , wherein the battery status is to indicate that a residual battery charge state is less than a normal threshold and greater than a reduced memory startup threshold, and wherein the map is to be associated with a low battery mapping scheme.

5. The computing system of claim 1 , wherein the instructions, when executed by the processor, further cause the processor to:
collect telemetry data during a configurable min-memory-startup mode, wherein the telemetry data is to be associated with the first set of ranks and the second set of ranks,
detect a change in the battery status,
enable the second set of ranks in response to the change, and
incorporate the second set of banks into the map in response to the change.

6. The computing system of claim 5 , wherein the change is to indicate that a residual battery charge state is greater than a normal threshold.

7. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
enable, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface;
disable, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface;
generate a map between a system address space and a first set of banks in the first set of ranks; and
exclude a second set of banks in the first set of ranks from the map.

8. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to:
monitor a write activity with respect to the first set of banks; and
disable refreshes in one or banks in the first set of banks based on the write activity.

9. The apparatus of claim 7 , wherein the user interface is to include a configuration object structure that defines one or more of memory properties, a memory configuration, a performance configuration, a user interface elements configuration, a storage configuration or a hot swap configuration.

10. The apparatus of claim 7 , wherein the battery status is to indicate that a residual battery charge state is less than a normal threshold and greater than a reduced memory startup threshold, and wherein the map is to be associated with a low battery mapping scheme.

11. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to:
collect telemetry data during a configurable min-memory-startup mode, wherein the telemetry data is to be associated with the first set of ranks and the second set of ranks;
detect a change in the battery status;
enable the second set of ranks in response to the change; and
incorporate the second set of banks into the map in response to the change.

12. The apparatus of claim 11 , wherein the change is to indicate that a residual battery charge state is greater than a normal threshold.

13. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

14. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
enable, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface;
disable, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface;
generate a map between a system address space and a first set of banks in the first set of ranks; and
exclude a second set of banks in the first set of ranks from the map.

15. The at least one non-transitory computer readable storage medium of claim 14 , wherein the instructions, when executed, further cause the computing system to:
monitor a write activity with respect to the first set of banks; and
disable refreshes in one or banks in the first set of banks based on the write activity.

16. The at least one non-transitory computer readable storage medium of claim 14 , wherein the user interface is to include a configuration object structure that defines one or more of memory properties, a memory configuration, a performance configuration, a user interface elements configuration, a storage configuration or a hot swap configuration.

17. The at least one non-transitory computer readable storage medium of claim 14 , wherein the battery status is to indicate that a residual battery charge state is less than a normal threshold and greater than a reduced memory startup threshold, and wherein the map is to be associated with a low battery mapping scheme.

18. The at least one non-transitory computer readable storage medium of claim 14 , wherein the instructions, when executed, further cause the computing system to:
collect telemetry data during a configurable min-memory-startup mode, wherein the telemetry data is to be associated with the first set of ranks and the second set of ranks;
detect a change in the battery status;
enable the second set of ranks in response to the change; and
incorporate the second set of banks into the map in response to the change.

19. The at least one non-transitory computer readable storage medium of claim 18 , wherein the change is to indicate that a residual battery charge state is greater than a normal threshold.

20. A method comprising:
enabling, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface;
disabling, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface;
generating a map between a system address space and a first set of banks in the first set of ranks; and
excluding a second set of banks in the first set of ranks from the map.

21. The method of claim 20 , further including:
monitoring a write activity with respect to the first set of banks; and
disabling refreshes in one or more banks in the first set of banks based on the write ac

Assignees

• Intel Corp

Inventors

• Kotary Karunakara
• Rajagopal Pannerkumar
• Muthiyalu Satish
• Poornachandran Rajesh

Classifications

• G06F9/4403 Primary

  Processor initialisation · CPC title

• G06F1/3212

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F9/451

  Execution arrangements for user interfaces · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title