Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

Patent metadata

Field	Value
Publication number	US-11921529-B2
Application number	US-202016914174-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Mar 13, 2013
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

First claim

What is claimed is:

1. An apparatus, comprising:
a first plurality of power drivers and a second plurality of power drivers coupled to a load to supply an output voltage to the load; and
a controller coupled to the first and second pluralities of power drivers, wherein the controller is to implement a first loop to provide fine control bits to the first plurality of power drivers according to a difference between a first reference voltage and the output voltage, and to implement a second loop to provide coarse control bits to the second plurality of power drivers according to a difference between a second reference voltage and the output voltage, wherein the fine control bits indicate a number of power drivers to turn on among the first plurality of power drivers, the coarse control bits indicate a number of power drivers to turn on among the second plurality of power drivers, and a current step size of the coarse control bits is greater than a current step size of the fine control bits.

2. The apparatus of claim 1 , wherein a sampling clock of the second loop is faster than a sampling clock of the first loop.

3. The apparatus of claim 1 , wherein the controller is to:
determine whether there is a voltage droop in the output voltage based on the difference between the first reference voltage and the output voltage, and the difference between the second reference voltage and the output voltage;
adjust the fine control bits but not the coarse control bits in response to determining the voltage droop is not detected; and
adjust the coarse control bits in response to determining the voltage droop is detected.

4. The apparatus of claim 1 , wherein the first and second pluralities of power drivers are partitioned such that they are positioned above and below the load.

5. The apparatus of claim 1 , wherein power drivers of the first plurality of power drivers are smaller than power drivers of the second plurality of power drivers.

6. The apparatus of claim 1 , wherein the first loop includes a first circuitry which operates on a first clock, the second loop includes a second circuitry which operates on a second clock, and a frequency of the second clock is higher than a frequency of the first clock.

7. The apparatus of claim 6 , wherein the frequency of the first clock is increased when the second loop operates to mitigate a voltage droop in the output voltage.

8. The apparatus of claim 1 , wherein the first loop and the second loop operate simultaneously.

9. The apparatus of claim 1 , wherein the first loop is to operate in steady-state condition of the apparatus, and wherein the second loop is to operate in a non-steady-state condition.

10. The apparatus of claim 1 , wherein the second reference voltage is lower than the first reference voltage.

11. The apparatus of claim 1 , wherein the second reference voltage is lower than the first reference voltage by about 20 mV or larger.

12. The apparatus of claim 1 , wherein:
the controller further comprises a first counter which outputs the fine control bits, a second counter which outputs the coarse control bits, and a logic unit coupled to the first counter and the second counter; and
the logic unit is to send a first signal to the first counter to generate the fine control bits and a second signal to the second counter to generate the coarse control bits.

13. The apparatus of claim 12 , wherein:
the controller comprises a first comparator to compare the first reference voltage and the output voltage, and a second comparator to compare the second reference voltage and the output voltage; and
the logic unit is to send the first signal in response to a voltage output from the first comparator and to send the second signal in response to a voltage output from the second comparator.

14. An apparatus, comprising:
a first set of power drivers to provide a first power supply to a load;
a second set of power drivers to provide a second power supply to the load; and
a circuit to provide a first loop to control a number of power drivers which are turned on among the first set of power drivers, and a second loop to control a number of power drivers which are turned on among the second set of power drivers, wherein:
when a voltage of the load is in a steady state condition, the first loop is to control the number of power drivers which are turned on among the first set of power drivers, while the second loop does not control the number of power drivers which are turned on among the second set of power drivers; and
when there is a droop in the voltage of the load, the second loop controls the number of power drivers which are turned on among the second set of power drivers to resolve the droop.

15. The apparatus of claim 14 , wherein the second loop adjusts the second power supply faster than the first loop adjusts the first power supply.

16. The apparatus of claim 14 , wherein:
the circuit comprises a logic unit;
the first loop comprises a first comparator which is to compare the voltage of the load to a first reference voltage and provide a respective output to the logic unit;
the second loop comprises a second comparator which is to compare the voltage of the load to a second reference voltage and provide a respective output to the logic unit;
the logic unit is to control the number of power drivers which are turned on among the first set of power drivers in response to the respective output of the first comparator; and
the logic unit is to control the number of power drivers which are turned on among the second set of power drivers in response to the respective output of the second comparator.

17. A system-on-chip, comprising:
a first set of N p-type devices coupled to a load to provide current to the load;
a second set of M p-type devices coupled to the load to provide current to the load, wherein N and M are integers;
a fine-grain counter coupled to the first set of N p-type devices to provide fine control bits to the first set of N p-type devices;
a coarse-grain counter coupled to the second set of M p-type devices to provide coarse control bits to the second set of M p-type devices, wherein one bit of the coarse control bits is to cause a larger current change in the second set of M p-type devices than a current change caused by one bit of the fine control bits in the first set of N p-type devices; and
a logic unit to send a first signal to the first counter to generate the fine control bits and a second signal to the second counter to generate the coarse control bits.

18. The system-on-chip of claim 17 , wherein N>M.

19. The system-on-chip of claim 17 , wherein the current change in the second set of M p-type devices caused by one bit of the coarse control bits is at least four times greater than the current change in the first set of N p-type devices caused by one bit of the fine control bits.

20. The system-on-chip of claim 17 , further comprising:
a first comparator to output a voltage indicative of a difference between a first reference voltage and a voltage of the load; and
a second comparator to output a voltage indicative of a difference between a second reference voltage and the voltage of the load, wherein the logic unit is to send the first signal in response to the voltage output from the first comparator and to send the second signal in response to the voltage output from the second comparator.

Assignees

• Intel Corp

Inventors

• Shih Yi-Chun
• Mazumdar Kaushik
• Kim Stephen T
• Jain Rinkle
• Tschanz James W
• Khellah Muhammad M

Classifications

• G05F1/563 Primary

  including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation · CPC title

• G05F1/46

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• G05F1/00

  Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title