Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

Patent metadata

Field	Value
Publication number	US-2019317536-A1
Application number	US-201916450873-A
Country	US
Kind code	A1
Filing date	Jun 24, 2019
Priority date	Jun 24, 2019
Publication date	Oct 17, 2019
Grant date	—

Abstract

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

First claim

What is claimed is:

1 . An apparatus of a hybrid linear dropout regulator (LDO) comprising:
a digital LDO that is coupled to a load of an integrated circuit (IC) at an output node, the digital LDO to provide an output voltage at the output node to supply power to the load; and an analog LDO that is coupled to the output node in parallel with the digital LDO, the analog LDO to provide a complementary voltage to the output node based on a noise in the output voltage; and wherein the digital LDO is coupled to a first rail to receive a first voltage and the analog LDO is coupled to a second rail to receive a second voltage, and wherein the first rail is different from the second rail.

2 . The apparatus of claim 1 , further comprising a digital regulator that is coupled to the analog LDO and the digital LDO to:
receive a gate voltage of the analog LDO; and generate a control signal to control the digital LDO, based on the gate voltage of the analog LDO.

3 . The apparatus of claim 2 , wherein the digital regulator is further to determine a value of the control signal based on respective comparisons of the gate voltage to a low reference and a high reference, wherein the low reference is smaller than the high reference.

4 . The apparatus of claim 3 , wherein the value of the control signal is a value of a sequence of bits based on which the digital LDO is operable to switch on at least one power transistor of an array of power transistors of the digital LDO, and the array of power transistors is arranged to provide a current supply to the load.

5 . The apparatus of claim 3 , wherein the low reference is a voltage reference V L , the V L is determined based at least in part on an input voltage of the analog LDO and a maximum value of a target power supply rejection ration (PSRR) of the output voltage.

6 . The apparatus of claim 3 , wherein the low reference is a voltage reference V L , the V L is determined based on a first equation of

V
L

=

V
mid

-

V
th

-

β
×

I

out
,
A

1

PSRR

D
,
max

-
1

V
DD

-

V
OUT

I
out

-

I

out
,
A

-

1

R
L

×

A

EA
,
DC

wherein V AA is an input voltage of the analog LDO, V th is a threshold voltage of a power transistor of the analog LDO, β is a resistor feedback factor of the analog LDO, I out,A is an output current provided by the analog LDO to the load, A EA,DC is a voltage gain of an error amplifier regarding a DC component, PSRR D,max is a maximum value of a target power supply rejection ration (PSRR) of the output voltage, V DD is an input voltage of the digital LDO, V OUT is the output voltage, I out is an output current to provide current to the load, and R L is a resistance of the load.

7 . The apparatus of claim 3 , wherein the high reference is a voltage reference V H , the V H is determined based at least in part on an input voltage of the analog LDO and a minimum value of a target power supply rejection ration (PSRR) of the output voltage.

8 . The apparatus of claim 3 , wherein the high reference is a voltage reference V H , the V H is determined based on a second equation of

V
H

=

V
mid

-

V
th

-

β
×

I

out
,
A

1

PSRR

D
,
min

-
1

V
DD

-

V
OUT

I
out

-

I

out
,
A

-

1

R
L

Assignees

• Intel Corp

Inventors

• Liu Xiaosen
• Krishnamurthy Harish
• Ravichandran Krishnan
• De Vivek
• Chiu Scott
• Barrera Gonzalez Claudia Patricia
• Han Jing
• Narayana Bhatla Rajasekhara Madhusudan

Classifications

• G05F1/467

  Sources with noise compensation · CPC title

• G05F1/59

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/595

  semiconductor devices connected in series · CPC title

• G05F1/563

  including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation · CPC title

• G05F1/462 Primary

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title