Display apparatus and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11917870-B2
Application number	US-202117328679-A
Country	US
Kind code	B2
Filing date	May 24, 2021
Priority date	Aug 14, 2020
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A display apparatus includes: a substrate including a first area, and a second area adjacent to the first area; a plurality of first pixel circuits at the first area of the substrate, each of the plurality of first pixel circuits including a silicon-based transistor, and an oxide-based transistor; a plurality of second pixel circuits at the second area of the substrate, the plurality of second pixel circuits including transistors; a first shielding layer at the first area, the first shielding layer including a shielding pattern overlapping with the silicon-based transistor of each of the plurality of first pixel circuits; and a second shielding layer at the second area, the second shielding layer including a first through-hole between adjacent second pixel circuits from among the plurality of second pixel circuits. The first shielding layer and the second shielding layer include different materials from each other.

First claim

What is claimed is:

1. A display apparatus comprising:
a substrate comprising a first area, and a second area adjacent to the first area;
a plurality of first pixel circuits at the first area of the substrate, each of the plurality of first pixel circuits comprising a silicon-based transistor, and an oxide-based transistor;
a plurality of second pixel circuits at the second area of the substrate, the plurality of second pixel circuits comprising transistors;
a plurality of first light-emitting diodes at the first area of the substrate, each of the plurality of first light-emitting diodes electrically connected to one of the plurality of first pixel circuits;
a plurality of second light-emitting diodes at the second area, each of the plurality of second light-emitting diodes electrically connected to one of the plurality of second pixel circuits;
a first shielding layer at the first area, the first shielding layer comprising a shielding pattern overlapping with the silicon-based transistor of each of the plurality of first pixel circuits; and
a second shielding layer at the second area between the substrate and the plurality of second pixel circuits, the second shielding layer comprising a first through-hole penetrating through the second shielding layer,
wherein the second area comprises a transmission area which is spaced apart from the plurality of second pixel circuits, and the first through-hole overlaps the transmission area, and
wherein the first shielding layer and the second shielding layer comprise different materials from each other.

2. The display apparatus of claim 1 , wherein the shielding pattern of the first shielding layer does not overlap with the oxide-based transistor of each of the plurality of first pixel circuits.

3. The display apparatus of claim 1 , wherein the shielding pattern of the first shielding layer has an isolated shape.

4. The display apparatus of claim 1 , wherein the first shielding layer comprises an amorphous silicon material that is doped with impurities.

5. The display apparatus of claim 1 , wherein the second shielding layer comprises a metal material.

6. The display apparatus of claim 1 , further comprising a buffer layer on the substrate, and located under the plurality of first pixel circuits and the plurality of second pixel circuits,
wherein the first shielding layer and the second shielding layer are between the substrate and the buffer layer.

7. The display apparatus of claim 1 , wherein the substrate comprises a first base layer, a first barrier layer, a second base layer, and a second barrier layer that are sequentially stacked, and
wherein the first shielding layer and the second shielding layer are between the second base layer and the second barrier layer.

8. The display apparatus of claim 1 , wherein the silicon-based transistor of each of the plurality of first pixel circuits comprises a semiconductor layer, and a gate electrode overlapping with a portion of the semiconductor layer, and
wherein a planar area of the shielding pattern of the first shielding layer is greater than a planar area of the gate electrode of the silicon-based transistor.

9. The display apparatus of claim 1 , wherein a thickness of the first shielding layer is less than a thickness of the second shielding layer.

10. The display apparatus of claim 1 , wherein each of the plurality of second pixel circuits comprises a silicon-based transistor, and an oxide-based transistor.

11. The display apparatus of claim 1 , further comprising a third shielding layer at the second area of the substrate, the third shielding layer comprising a material different from that of the second shielding layer.

12. The display apparatus of claim 11 , wherein the third shielding layer corresponds to the second shielding layer, and comprises a second through-hole overlapping with the first through-hole of the second shielding layer.

13. The display apparatus of claim 11 , wherein the third shielding layer comprises a same material as that of the first shielding layer.

14. A display apparatus comprising:
a substrate comprising a first area and a second area adjacent to the first area;
a plurality of first light-emitting diodes at the first area of the substrate;
a plurality of second light-emitting diodes at the second area of the substrate;
a plurality of first pixel circuits at the first area of the substrate, each of the plurality of first pixel circuits comprising a silicon-based transistor and an oxide-based transistor, and one of the plurality of first pixel circuits electrically connected to one of the plurality of first light-emitting diodes;
a plurality of second pixel circuits on the substrate, one of the plurality of second pixel circuits electrically connected to at least one of the plurality of second light-emitting diodes;
a first shielding layer at the first area between the substrate and the plurality of first light-emitting diodes, the first shielding layer comprising a shielding pattern overlapping with each of the plurality of first pixel circuits, the first shielding layer comprising an amorphous silicon material;
a second shielding layer at the second area between the substrate and the plurality of second light-emitting diodes, the second shielding layer comprising a metal material; and
an electronic component overlapping the second area,
wherein a transmittance of the second area is greater than a transmittance of the first area.

15. The display apparatus of claim 14 , wherein the shielding pattern of the first shielding layer overlaps with the silicon-based transistor and does not overlap with the oxide-based transistor of each of the plurality of first pixel circuits.

16. The display apparatus of claim 14 , wherein the shielding pattern of the first shielding layer has an isolated shape.

17. The display apparatus of claim 14 , further comprising a buffer layer on the substrate, and located under the plurality of first pixel circuits and the plurality of second pixel circuits,
wherein the first shielding layer and the second shielding layer are between the substrate and the buffer layer.

18. The display apparatus of claim 14 , wherein the substrate comprises a first base layer, a first barrier layer, a second base layer, and a second barrier layer that are sequentially stacked, and
wherein the first shielding layer and the second shielding layer are between the second base layer and the second barrier layer.

19. The display apparatus of claim 14 , wherein the silicon-based transistor of each of the plurality of first pixel circuits comprises a semiconductor layer, and a gate electrode overlapping with a portion of the semiconductor layer, and
wherein a planar area of the shielding pattern of the first shielding layer is greater than a planar area of the gate electrode of the silicon-based transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Kyunghyun
• Ko Moosoon
• Jung Jingoo
• Jung Sugwoo

Classifications

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title

• H10K59/12 Primary

  Active-matrix OLED [AMOLED] displays · CPC title

• H10K59/8792

  comprising light absorbing layers, e.g. black layers · CPC title

• H10K59/126 Primary

  Shielding, e.g. light-blocking means over the TFTs · CPC title