Multiprocessor programming toolkit for design reuse

US11914989B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11914989-B2
Application numberUS-202117513336-A
CountryUS
Kind codeB2
Filing dateOct 28, 2021
Priority dateNov 6, 2012
Publication dateFeb 27, 2024
Grant dateFeb 27, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may specify one or more cell definitions that include: program instructions executable to perform a function and one or more language constructs. The software code may further instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, where the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports and the first and second cell instances are included in the third cell instance.

First claim

Opening claim text (preview).

What is claimed is: 1. A non-transitory computer-readable medium that stores software code deployable on a multiprocessor array (MPA), wherein the software code comprises a set of program instructions that: specify one or more cell definitions that include: program instructions executable to perform a function; and one or more language constructs; and instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, wherein the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports; the first and second cell instances are included in the third cell instance; a communication port of the first cell instance is coupled to a first communication port of the third cell instance; and a communication port of the second cell instance is coupled to a second communication port of the third cell instance different from the first communication port of the third cell instance. 2. The non-transitory computer-readable medium of claim 1 , wherein the first cell instance includes one or more other cell instances. 3. The non-transitory computer-readable medium of claim 1 , wherein the first and third cell instances are instances of different cell definitions. 4. The non-transitory computer-readable medium of claim 1 , wherein the first and third cell instances are instances of the same cell definition but are configured to use different amounts of hardware resources of the MPA. 5. The non-transitory computer-readable medium of claim 1 , wherein the cell definition for the third cell instance specifies that it includes one or more cell instances. 6. The non-transitory computer-readable medium of claim 1 , wherein the one or more language constructs configure the third cell instance to include the first and second cell instances. 7. The non-transitory computer-readable medium of claim 1 , wherein the first and second cell instances are configured to communicate current hardware resource usage. 8. The non-transitory computer-readable medium of claim 1 , wherein the communication ports are mappable to dynamic routing circuitry of the MPA that routes communications between processing element of the MPA. 9. A method for configuring a multiprocessor array (MPA), wherein the MPA comprises hardware resources including a plurality of processors and a plurality of memories, the method comprising: accessing software code, wherein the software code a set of program instructions that: specify one or more cell definitions that include: program instructions executable to perform a function; and one or more language constructs; and instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, wherein the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports; the first and second cell instances are included in the third cell instance; a communication port of the first cell instance is coupled to a first communication port of the third cell instance; and a communication port of the second cell instance is coupled to a second communication port of the third cell instance different from the first communication port of the third cell instance; and deploying the first, second, and third cell instances on the MPA. 10. The method of claim 9 , wherein the first cell instance includes one or more other cell instances. 11. The method of claim 9 , wherein the cell definition for the third cell instance specifies that it includes one or more cell instances. 12. The method of claim 9 , wherein the one or more language constructs configure the third cell instance to include the first and second cell instances. 13. The method of claim 9 , further comprising: dynamically adjusting an amount of hardware resources of the MPA that is assigned to the first cell instance. 14. The method of claim 9 , wherein the first and second cell instances are configured to communicate current hardware resource usage. 15. A system, comprising: one or more processors; and one or more memories having program instructions stored thereon that are executable to deploy software code on a multiprocessor array (MPA), wherein the software code comprises a set of program instructions that: specify one or more cell definitions that include: program instructions executable to perform a function; and one or more language constructs; and instantiate first, second, and third cell instances, each of which is an instantiation of one of the one or more cell definitions, wherein the instantiation includes configuration of the one or more language constructs such that: the first and second cell instances communicate via respective communication ports; the first and second cell instances are included in the third cell instance; a communication port of the first cell instance is coupled to a first communication port of the third cell instance; and a communication port of the second cell instance is coupled to a second communication port of the third cell instance different from the first communication port of the third cell instance. 16. The system of claim 15 , wherein the first cell instance includes one or more other cell instances. 17. The system of claim 15 , wherein the one or more language constructs configure the third cell instance to include the first and second cell instances. 18. The system of claim 15 , wherein the deployment maps communication to dynamic routing circuitry of the MPA that is configured to routes communications between processing element of the MPA. 19. The system of claim 15 , wherein the cell definition for the third cell instance specifies that it includes one or more cell instances. 20. The system of claim 15 , wherein the first and second cell instances are configured to communicate current hardware resource usage.

Assignees

Inventors

Classifications

  • G06F8/71Primary

    Version control (security arrangements therefor G06F21/57); Configuration management · CPC title

  • Optimisation · CPC title

  • Software deployment · CPC title

  • Configuring for program initiating, e.g. using registry, configuration files · CPC title

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What does patent US11914989B2 cover?
Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may specify one or more cell …
Who is the assignee on this patent?
Coherent Logix Inc
What technology area does this patent fall under?
Primary CPC classification G06F8/71. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 27 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).