Array substrate and manufacturing method thereof, display panel

Patent metadata

Field	Value
Publication number	US-11914253-B2
Application number	US-202318092581-A
Country	US
Kind code	B2
Filing date	Jan 3, 2023
Priority date	Jan 14, 2019
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

Embodiments of the present disclosure provides an array substrate and a manufacturing method thereof, a display panel. The array substrate includes: a base ( 10 ); a pixel electrode ( 50 ) and a thin film transistor disposed on the base ( 10 ); a passivation layer ( 16 ) covering the thin film transistor and the pixel electrode ( 50 ), the passivation layer ( 16 ) being provided with a transferring through hole (K 1 , K 2 ) that simultaneously exposes the pixel electrode ( 50 ) and a drain electrode ( 15 ) or a source electrode ( 14 ) of the thin film transistor; a connection electrode ( 60 ) disposed on the passivation layer ( 16 ) and at the transferring through hole (K 1 , K 2 ), the connection electrode ( 60 ) connected with the pixel electrode ( 50 ), and the drain electrode ( 15 ) or the source electrode ( 14 ) through the transferring through hole (K 1 , K 2 ). The present disclosure realizes a connection between the drain electrode ( 15 ) or the source electrode ( 14 ) and the pixel electrode ( 50 ) by using one transferring through hole (K 1 , K 2 ), which effectively reduces the number of through holes, increases an aperture ratio of the display panel, improves product quality and yield.

First claim

What is claimed is:

1. An array substrate, comprising
a base;
a pixel electrode and a thin film transistor, disposed on the base;
a passivation layer, covering the thin film transistor and the pixel electrode, the passivation layer being provided with a transferring through hole exposing the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously;
a connection electrode, disposed on the passivation layer and at the transferring through hole,
wherein the connection electrode is connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole,
wherein the array substrate further comprises a gate line and a data line, the thin film transistor comprises a gate electrode, an active layer, the source electrode and the drain electrode, the pixel electrode, the gate line and the gate electrode are disposed on the base, the pixel electrode, the gate line and the gate electrode are covered with a gate insulation layer, the active layer, the source electrode, the drain electrode and the data line are disposed on the gate insulation layer, and a conductive channel is formed between the source electrode and the drain electrode,
wherein a first compensation block is disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base,
wherein the first compensation block extends from a mainbody of the connection electrode towards the gate line, and a size of the first compensation block is smaller than a size of the mainbody in a direction parallel to a direction of the gate line.

2. The array substrate according to claim 1 , wherein an orthographic projection of the transferring through hole on the base overlaps with an orthographic projection of the pixel electrode on the base and an orthographic projection of the drain electrode or the source electrode on the base.

3. The array substrate according to claim 1 , wherein an second compensation block is disposed at a side of the connection electrode away from the gate line, an orthographic projection of the second compensation block on the base includes at least a portion of an orthographic projection of an edge of the source electrode or the drain electrode at a side away from the gate line on the base.

4. The array substrate according to claim 3 , wherein the second compensation block extends from the mainbody of the connection electrode to a direction away from the gate line, and a size of the second compensation block is smaller than a size of the mainbody in a direction parallel to a direction of the gate line.

5. The array substrate according to claim 4 , wherein an orthographic projection of the connection electrode on the base covers an orthographic projection of an overlapped region between the drain electrode or the source electrode and the pixel electrode on the base.

6. The array substrate according to claim 1 , wherein a shape of the first compensation block comprises a rectangle, a trapezoid, a semicircle or a semi-ellipse.

7. The array substrate according to claim 3 , a shape of the second compensation block comprises a rectangle, a trapezoid, a semicircle or a semi-ellipse.

8. The array substrate according to claim 1 , wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the first through hole portion exposes the drain electrode, the second through hole portion exposes the pixel electrode.

9. A display panel comprising the array substrate according to claim 1 .

10. A manufacturing method of an array substrate, comprising:
forming a pixel electrode and a thin film transistor;
forming a passivation layer covering the thin film transistor, the passivation layer being provided with a transferring through hole that exposes the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously;
forming a connection electrode on the passivation layer and at the transferring through hole, wherein the connection electrode is simultaneously connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole,
wherein the forming a pixel electrode and a thin film transistor on the base comprises:
forming the pixel electrode, a gate line and a gate electrode by means of one patterning process;
forming a gate insulation layer, an active layer, a source electrode, a drain electrode and a data line by means of one patterning process, forming a conductive channel between the source electrode and the drain electrode,
wherein a first compensation block is disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base, the first compensation block extends from a mainbody of the connection electrode towards the gate line, and a size of the first compensation block is smaller than a size of the mainbody in a direction parallel to a direction of the gate line.

11. The manufacturing method according to claim 10 , wherein a second compensation block is disposed at a side of the connection electrode away from the gate line, an orthographic projection of the second compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side away from the gate line on the base.

12. The manufacturing method according to claim 11 , wherein a size of the second compensation block is smaller than a size of the mainbody in a direction parallel to a direction of the gate line.

13. The manufacturing method according to claim 10 , wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the first through hole portion exposes the drain electrode, and the second through hole portion exposes the pixel electrode.

14. The manufacturing method according to claim 10 , wherein the forming a pixel electrode, a gate line and a gate electrode by means of one patterning process comprises:
depositing a first transparent conductive film and a first metal film on the base sequentially;
coating a layer of photoresist on the first metal film, gradient exposing and developing the photoresist using a halftone mask or a gray tone mask, forming an unexposed region at a location where the gate line and the gate electrode to be formed are located, the unexposed region being with a photoresist having a first thickness, forming a partially exposed region at a location where the pixel electrode to be formed is located, the partially exposed region being with a photoresist having a second thickness, forming a fully exposed region at other locations without a photoresist, and the first thickness is greater than the second thickness;
etching away the first metal film and the first transparent conductive film in the fully exposed region by means of a first etching process;
removing the photoresist in the partially exposed region by means of an ashing process, exposing the first metal film; and
etching away the first metal film in the partially exposed region by means of a second etching process, removing a remaining portion of the photoresist and forming the pixel electrode, the gate line a

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Xiaoyuan
• Wang Wu
• Fang Yan
• Wu Shengxue

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title