Methods and systems for calibrating clock skew in a receiver

Patent metadata

Field	Value
Publication number	US-11909853-B2
Application number	US-202217696406-A
Country	US
Kind code	B2
Filing date	Mar 16, 2022
Priority date	Dec 17, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.

First claim

What is claimed is:

1. A method for performing calibration on a clock skew in a receiver, the method comprising:
repeatedly sampling, by the receiver, a skew in an edge of a clock with respect to an edge of a reference clock, to obtain a plurality of first values sampled by the clock and a plurality of second values sampled by the reference clock at edges of a data pattern;
determining, by the receiver, a count associated with the skew from a de-serialized data word, wherein the de-serialized data word comprises a plurality of outcome values obtained based on the plurality of first values sampled by the clock and the plurality of second values sampled by the reference clock, at a predefined number of the edges of the data pattern;
obtaining, by the receiver, a skew calibration code corresponding to a first Phase Interpolator (PI) code, from a binary variable, wherein the binary variable is obtained by accumulating an encoded variable generated based on the count associated with the skew in the de-serialized data word to a previously generated binary variable; and
calibrating, by the receiver, the skew in the edge of the clock by performing one of a positive phase shift or a negative phase shift to the clock based on the skew calibration code, to align edges of the clock with the edges of the data pattern and edges of the reference clock,
wherein the clock is an edge sampling clock, and the edge sampling clock samples at edges of the data pattern.

2. The method as claimed in claim 1 , wherein the receiver comprises a data sampler, and positive edges of the edge sampling clock are used by the data sampler to sample the edges of data pulses in the data pattern.

3. The method as claimed in claim 1 , wherein the reference clock is an edge sampling clock, and
wherein the reference clock samples the edges of the data pattern.

4. The method as claimed in claim 1 , wherein the skew is one of a positive skew and a negative skew, and
wherein each of the plurality of outcome values in the de-serialized data word indicates at least one from among the positive skew, the negative skew, and an absence of skew.

5. The method as claimed in claim 4 , wherein the encoded variable is determined as a positive binary one based on a count of the positive skew indicated in the de-serialized data word being greater than a count of the negative skew indicated in the de-serialized data word.

6. The method, as claimed in claim 4 , wherein the encoded variable is determined as a negative binary one based on a count of the positive skew indicated in the de-serialized data word being less than a count of the negative skew indicated in the de-serialized data word.

7. The method, as claimed in claim 4 , wherein the encoded variable is determined as zero based on a count of the positive skew indicated in the de-serialized data word being equal to a count of the negative skew indicated in the de-serialized data word.

8. The method as claimed in claim 1 , wherein the skew calibration code is obtained by extracting a predefined number of bits from the binary variable, and
wherein the binary variable and the previously generated binary variable are 16-bit binary numbers, and the previously generated binary variable is obtained by accumulating encoded variables generated from previous de-serialized words.

9. The method as claimed in claim 8 , wherein the positive phase shift and the negative phase shift are performed on the clock based on the predefined number of bits of the skew calibration code.

10. The method as claimed in claim 8 , wherein the positive phase shift is performed on the clock based on the skew calibration code being less than a previously generated skew calibration code, and
wherein the negative phase shift is performed on the clock based on the skew calibration code being more than the previously generated skew calibration code.

11. The method as claimed in claim 8 , wherein 6-bits from most significant bits (MSB) of the binary variable is extracted from the binary variable to create the skew calibration code.

12. The method as claimed in claim 1 , wherein the method further comprises:
changing, by the receiver, from a first eye opening margin (EOM) PI code to a second EOM PI code; and
obtaining, by the receiver, a predefined number of skew calibration codes corresponding to a predefined number of PI codes, wherein the predefined number of PI codes are based on the second EOM PI code.

13. The method as claimed in claim 12 , wherein the method further comprises obtaining, by the receiver, an average skew calibration code by computing an average of the predefined number of skew calibration codes.

14. The method as claimed in claim 1 , wherein the calibrating comprises aligning the edges of the reference clock to edges of a complementary data pattern.

15. An apparatus for performing calibration on a clock skew, comprising:
at least one processor configured to:
repeatedly sample a skew in an edge of a clock with respect to an edge of a reference clock, to obtain a plurality of first values sampled by the clock and a plurality of second values sampled by the reference clock at edges of a data pattern;
determine a count associated with the skew from a de-serialized data word, wherein the de-serialized data word comprises a plurality of outcome values obtained based on the plurality of first values sampled by the clock and the plurality of second values sampled by the reference clock, at a predefined number of the edges of the data pattern;
obtain a skew calibration code corresponding to a first Phase Interpolator (PI) code, from a binary variable, wherein the binary variable is obtained by accumulating an encoded variable generated based on the count associated with the skew in the de-serialized data word to a previously generated binary variable; and
calibrate the skew in the edge of the clock by performing one of a positive phase shift or a negative phase shift to the clock based on the skew calibration code, to align edges of the clock with the edges of the data pattern and edges of the reference clock.

16. The apparatus as claimed in claim 15 , wherein the skew in the edge of the clock is one of a positive skew and a negative skew, and
wherein each of the plurality of outcome values in the de-serialized data word indicates at least one from among the positive skew, the negative skew, and an absence of skew.

17. The apparatus as claimed in claim 16 , wherein the at least one processor is further configured to:
obtain the skew calibration code by extracting a predefined number of bits from the binary variable,
wherein the binary variable and the previously generated binary variable are 16-bit binary numbers, and the previously generated binary variable is obtained by accumulating encoded variables generated from previous de-serialized words.

18. The apparatus as claimed in claim 17 , wherein the at least one processor is further configured to perform the positive phase shift and the negative phase shift on the clock based on the predefined number of bits of the skew calibration code.

19. The apparatus as claimed in claim 17 , wherein the at least one processor is further configured to:
perform the positive phase shift on the clock based on the skew calibration code being less than a previously generated skew calibration code, and
perform the negative phase shift on the clock based on the skew calibration code being more than the previously generated skew calibration code.

20. A non-transitory computer-readable storage

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hazra Saikat
• Verma Avneesh Singh
• Molthati Raghavendra
• Rajan Sunil
• Das Tamal
• Garg Ankit
• Bharadwaj Praveen S
• Ghosh Sanjeeb Kumar

Classifications

• H04L7/0016 Primary

  correction of synchronization errors · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H04L7/0025 Primary

  interpolation of clock signal · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title