Thin film transistors with raised source and drain contacts and process for forming such

Patent metadata

Field	Value
Publication number	US-11908911-B2
Application number	US-201916414481-A
Country	US
Kind code	B2
Filing date	May 16, 2019
Priority date	May 16, 2019
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.

First claim

What is claimed is:

1. A device, comprising:
a source contact in a source contact trench and a drain contact in a drain contact trench;
a channel layer under the source contact and the drain contact, the channel layer having a first depression in a source region beneath the source contact, and the channel layer having a second depression in a drain region beneath the drain contact;
a first spacing layer on a bottom of the source contact and in the first depression in the channel layer, and a second spacing layer on a bottom of the drain contact and in the second depression in the channel layer, wherein the first spacing layer and the second spacing layer are on a surface of the channel layer, each of the first spacing layer and the second spacing layer having a central deeper portion laterally between outer shallower portions, each of the source contact and the drain contact having an upper portion wider than a bottom portion in the respective source contact trench and the drain contact trench;
a gate electrode below the channel layer;
a dielectric above the gate electrode and underneath the channel layer; and
wherein the first spacing layer and the second spacing layer extend a distance of 15 to 30 nm up along sides of the source contact trench and the drain contact trench.

2. The device of claim 1 , wherein a bottom surface of the source contact and a bottom surface of the drain contact is above the first spacing layer and the second spacing layer, respectively, and above the surface of the channel layer.

3. The device of claim 1 , wherein the first spacing layer and the second spacing layer include portions that extend partially up the sides of the source contact trench and partially up the sides of the drain contact trench.

4. The device of claim 1 , wherein the first spacing layer and the second spacing layer include a semiconductor.

5. The device of claim 1 , wherein the first spacing layer and the second spacing layer include an insulator.

6. The device of claim 1 , wherein the first spacing layer and the second spacing layer include oxide.

7. The device of claim 1 , wherein the thickness of the first spacing layer and the thickness of the second spacing layer is 1-5 nm.

8. The device of claim 1 , wherein the source contact and the drain contact include a work function metal.

9. The device of claim 1 , wherein the source contact and the drain contact include a plurality of layers of conductors.

10. The device of claim 1 , wherein the source contact and the drain contact include a single conductor.

11. A device, comprising:
a source contact and a drain contact in a source contact trench and a drain contact trench;
a channel layer under the source contact and the drain contact, the channel layer having a first depression in a source region beneath the source contact, and the channel layer having a second depression in a drain region beneath the drain contact;
a first spacing layer on a bottom of the source contact and in the first depression in the channel layer, and a second spacing layer on a bottom of the drain contact and in the second depression in the channel layer, wherein the first spacing layer and the second spacing layer are on a surface of the channel layer and line sidewalls of the source contact trench and the drain contact trench each of the first spacing layer and the second spacing layer having a central deeper portion laterally between outer shallower portions, each of the source contact and the drain contact having an upper portion wider than a bottom portion in the respective source contact trench and the drain contact trench;
a gate electrode below the channel layer; and
a dielectric above the gate electrode and underneath the channel layer; and
wherein the first spacing layer and the second spacing layer extend a distance of 15 to 30 nm up along sides of the source contact trench and the drain contact trench.

12. The device of claim 11 , wherein a bottom surface of the source contact and a bottom surface of the drain contact is above the first spacing layer and the second spacing layer, respectively, and above the surface of the channel layer.

13. The device of claim 11 , wherein the first spacing layer and the second spacing layer is a semiconductor or an insulator.

Assignees

• Intel Corp

Inventors

• Ku Chieh-Jen
• Sell Bernhard
• Wang Pei-Hua

Classifications

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D64/512 Primary

  Disposition of the gate electrodes, e.g. buried gates · CPC title