Method for fabricating GaN chip and GaN chip

Patent metadata

Field	Value
Publication number	US-11908689-B2
Application number	US-202118268949-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Jul 15, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb 2 N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb 2 N sacrificial layer; growing a Ta 2 N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta 2 N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer; and transferring remaining material after removal of the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

First claim

The invention claimed is:

1. A method for fabricating a GaN chip, comprising:
growing a Nb 2 N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb 2 N sacrificial layer;
growing a Ta 2 N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta 2 N sacrificial layer to form a GaN wafer;
bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer; and
transferring remaining material after removal of the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

2. The method according to claim 1 , wherein growing the Nb 2 N sacrificial layer on the original substrate comprises:
fabricating the Nb 2 N sacrificial layer with a thickness of 0-50 nm on the original substrate.

3. The method according to claim 1 , wherein growing the Ta 2 N sacrificial layer on the GaN insertion layer comprises:
fabricating the Ta 2 N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.

4. The method according to claim 1 , wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.

5. The method according to claim 4 , wherein coating the first surface of the temporary carrier with the adhesive material comprises:
coating the first surface of the temporary carrier with the adhesive material by a spin coating method, and controlling a rotation speed to be 1200-3000 rpm and a time to be 30-60 seconds.

6. The method according to claim 4 , wherein placing the temporary carrier on the hot plate for baking comprises:
controlling the temperature of the hot plate to 120° C. and baking for 3 minutes; and
controlling the temperature of the hot plate to 180° C. and baking for 4 minutes.

7. The method according to claim 1 , wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.

8. The method according to claim 1 , wherein removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer comprises:
removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1.

9. The method according to claim 1 , wherein transferring the remaining material after removal of the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer to the target substrate comprises:
activating the remaining material and the target substrate with nitrogen or oxygen, aligning the activated target substrate with the activated remaining material for attachment, and carrying out annealing.

10. A chip, fabricated by the method according to claim 1 .

11. The method according to claim 1 , wherein the material of the original substrate is one of SiC, GaN, sapphire, diamond, Ga 2 O 3 and AlN.

12. The method according to claim 1 , wherein in the step of growing the Ta 2 N sacrificial layer on the GaN insertion layer, the Ta 2 N sacrificial layer with hexagonal crystal structure symmetry is grown on the GaN insertion layer by thin film deposition.

13. The method according to claim 1 , wherein in the step of bonding the GaN wafer with the first surface of the temporary carrier, the wafer bonding is carried out through a wafer bonding machine, a bonding temperature is 150-200° C., a bonding time is 5-10 min, and a pressure is 0.1 MPa.

14. The method according to claim 8 , wherein in the step of removing the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer, the Nb 2 N sacrificial layer and the Ta 2 N sacrificial layer are removed by a selective wet chemical etching, the original substrate is separated from the GaN insertion layer after etching.

15. The chip according to claim 10 , wherein growing the Nb 2 N sacrificial layer on the original substrate comprises:
fabricating a Nb 2 N sacrificial layer with a thickness of 0-50 nm on the original substrate.

16. The chip according to claim 10 , wherein growing the Ta 2 N sacrificial layer on the GaN insertion layer comprises:
fabricating the Ta 2 N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.

17. The chip according to claim 10 , wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.

18. The chip according to claim 17 , wherein coating the first surface of the temporary carrier with the adhesive material comprises:
coating the first surface of the temporary carrier with the adhesive material by a spin coating method, and controlling a rotation speed to be 1200-3000 rpm and a time to be 30-60 seconds.

19. The chip according to claim 17 , wherein placing the temporary carrier on the hot plate for baking comprises:
controlling the temperature of the hot plate to 120° C. and baking for 3 minutes; and
controlling the temperature of the hot plate to 180° C. and baking for 4 minutes.

20. The chip according to claim 10 , wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.

Assignees

• Inspur Suzhou Intelligent Technology Co Ltd

Inventors

• Guo Fen
• Su kang
• Zhou Lang
• Li Tuo
• Man Hongtao

Classifications

• H10P95/11

  Separation of active layers from substrates · CPC title

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10W20/058

  by depositing on sacrificial masks, e.g. using lift-off · CPC title

• H10P14/3416 Primary

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title