Epitaxial metallic transition metal nitride layers for compound semiconductor devices

US10340353B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10340353-B2
Application numberUS-201514813460-A
CountryUS
Kind codeB2
Filing dateJul 30, 2015
Priority dateAug 1, 2014
Publication dateJul 2, 2019
Grant dateJul 2, 2019

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Abstract

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A method for integrating epitaxial, metallic transition metal nitride (TMN) layers within a compound semiconductor device structure. The TMN layers have a similar crystal structure to relevant semiconductors of interest such as silicon carbide (SiC) and the Group III-Nitrides (III-Ns) such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their various alloys. Additionally, the TMN layers have excellent thermal stability and can be deposited in situ with other semiconductor materials, allowing the TMN layers to be buried within the semiconductor device structure to create semiconductor/metal/semiconductor heterostructures and superlattices.

First claim

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What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. A method for integrating epitaxial metallic transition metal nitride (TMN) layers within a semiconductor device, comprising: providing a substrate; growing an epitaxial metal layer selected from the group consisting of TaN x , NbN x , WN x , MoN x , TMN ternary compounds, and combinations thereof; and growing at least one epitaxial semiconductor layer comprising a semiconductor material selected from the group consisting of SiC or AlN; wherein the in-plane lattice constants of the substrate, the epitaxial metal layer, and the epitaxial semiconductor layer are all within 2% of one another; and wherein the epitaxial metal layer is grown directly on the substrate and the at least one epitaxial semiconductor layer is grown directly on the epitaxial metal layer to form an epitaxial metal/semiconductor heterostructure, or the at least one epitaxial semiconductor layer is grown directly on the substrate and the epitaxial metal layer is grown directly on the at least one epitaxial semiconductor layer to form an epitaxial metal/semiconductor heterostructure. 2. The method of claim 1 , wherein the epitaxial metal layer and the at least one epitaxial semiconductor layer are grown in situ. 3. The method of claim 1 , wherein the epitaxial metal layer is selected from the group consisting of Ta 2 N, Nb 2 N, and combinations thereof. 4. The method of claim 1 , wherein the substrate is selected from the group consisting of SiC, GaN, AlN, and combinations thereof. 5. The method of claim 1 , additionally comprising a second epitaxial metal layer on top of the at least one epitaxial semiconductor layer, wherein the second epitaxial metal layer may be of different material composition or stoichiometry from the epitaxial metal layer. 6. The method of claim 1 , additionally comprising additional multiple layers of epitaxial metal layers and epitaxial semiconductor layers, wherein the additional layers may be of different material composition or stoichiometry. 7. The method of claim 1 , wherein the epitaxial metal layer and epitaxial semiconductor layer have hexagonal crystal structures. 8. The method of claim 1 , wherein the epitaxial metal/semiconductor heterostructure is selected from the group consisting of a buried contact, a quantum well, a buried mirror, a cladding layer, and a superlattice. 9. A semiconductor device, comprising: a substrate; an epitaxial metal layer selected from the group consisting of TaN x , NbN x , WN x , MoN x , TMN ternary compounds, and combinations thereof; and at least one epitaxial semiconductor layer comprising a semiconductor material selected from the group consisting of SiC or AlN; wherein the in-plane lattice constants of the substrate, the epitaxial metal layer, and the epitaxial semiconductor layer are within 2% of one another; and wherein the epitaxial metal layer is in direct contact with the substrate and the at least one epitaxial semiconductor layer is in direct contact with the epitaxial metal layer to form an epitaxial metal/semiconductor heterostructure, or the at least one epitaxial semiconductor layer is in direct contact with the substrate and the epitaxial metal layer is in direct contact with the at least one epitaxial semiconductor layer to form an epitaxial metal/semiconductor heterostructure. 10. The semiconductor device of claim 9 , wherein the epitaxial metal layer and the at least one epitaxial semiconductor layer are grown in situ. 11. The semiconductor device of claim 9 , wherein the epitaxial metal layer is selected from the group consisting of Ta 2 N, Nb 2 N, and combinations thereof. 12. The semiconductor device of claim 9 , wherein the substrate is selected from the group consisting of SiC, GaN, AlN, and combinations thereof. 13. The semiconductor device of claim 9 , additionally comprising a second epitaxial metal layer on top of the at least one epitaxial semiconductor layer, wherein the second epitaxial metal layer may be of different material composition or stoichiometry from the epitaxial metal layer. 14. The semiconductor device of claim 9 , additionally comprising additional multiple layers of epitaxial metal layers and epitaxial semiconductor layers, wherein the additional layers may be of different material composition or stoichiometry. 15. The semiconductor device of claim 9 , wherein the epitaxial metal layer and epitaxial semiconductor layer have hexagonal crystal structures. 16. The semiconductor device of claim 9 , wherein the epitaxial metal/semiconductor heterostructure is selected from the group consisting of a buried contact, a quantum well, a buried mirror, a cladding layer, and a superlattice.

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What does patent US10340353B2 cover?
A method for integrating epitaxial, metallic transition metal nitride (TMN) layers within a compound semiconductor device structure. The TMN layers have a similar crystal structure to relevant semiconductors of interest such as silicon carbide (SiC) and the Group III-Nitrides (III-Ns) such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their various alloys. Addition…
Who is the assignee on this patent?
Meyer David J, Downey Brian P, Katzer Douglas S, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10P14/3416. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 02 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).