First-pass continuous read level calibration

Patent metadata

Field	Value
Publication number	US-11908536-B2
Application number	US-202217982346-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Sep 5, 2018
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device then adjusts a read level threshold of the memory cell to be centered between a first programming distribution and a second programming distribution before the second programming pass of the programming operation is performed on the memory cell.

First claim

What is claimed is:

1. A system comprising:
a memory component; and
a processing device, operatively coupled with the memory component, to:
determine that a first programming pass of a programming operation has been performed on a memory cell of the memory component; and
adjust a read level threshold of the memory cell to be centered between a first programming distribution and a second programming distribution before a second programming pass of the programming operation is performed on the memory cell.

2. The system of claim 1 , wherein the processing device is further to perform the second programming pass of the programming operation on the memory cell.

3. The system of claim 1 , wherein the processing device is further to:
determine information about a valley between the first programming distribution and the second programming distribution before the second programming pass of the program operation is performed on the memory cell, wherein the processing device is to adjust the read level threshold of the memory cell responsive to determining the information.

4. The system of claim 1 , wherein the processing device is further to:
adjust a second read level threshold of the memory cell to be centered between the second programming distribution and a third programming distribution before the second programming pass of the programming operation is performed on the memory cell.

5. The system of claim 1 , wherein the processing device is further to:
determine second information about each valley between each pair of a plurality of first-pass programming distributions before the second programming pass of the programming operation is performed on the memory cell; and
adjust, using the second information, each read level threshold to be centered between each pair of the plurality of first-pass programming distributions before the second programming pass of the programming operation is performed on the memory cell.

6. The system of claim 1 , wherein the processing device is further to:
adjust a second read level threshold of the memory cell to be centered between the second programming distribution and a third programming distribution after the second programming pass of the programming operation is performed on the memory cell.

7. The system of claim 1 , wherein the processing device is further to:
iteratively perform a read operation on the memory cell;
iteratively measure a bit error rate (BER) of the memory cell; and
adjust the read level threshold of the memory cell based on the BER of the memory cell to center the read level threshold between the first programming distribution and the second programming distribution.

8. The system of claim 1 , wherein the processing device is further to:
calculate a center bit error count;
calculate a difference error count;
adjust the read level threshold of the memory cell based on the center bit error count and the difference error count; and
store the center bit error count and the difference error count for the read level threshold.

9. The system of claim 1 , wherein the memory component comprises a block comprising a plurality of memory cells organized in a plurality of wordline groups, wherein the memory cell is a sample cell of a first wordline group of the plurality of wordline groups.

10. The system of claim 9 , wherein the block further comprises a second sample memory cell of a second wordline group of the plurality of wordline groups, wherein the processing device is further to:
determine that the first programming pass has been performed on the second sample memory cell; and
adjust a second read level threshold of the second sample memory cell to be centered between a third programming distribution and a fourth programming distribution before the second programming pass of the programming operation is performed on the second sample memory cell.

11. The system of claim 1 , wherein the memory component comprises a first block comprising the memory cell and a second block comprising a second memory cell, and wherein the processing device is further to:
determine that the first programming pass has been performed on a second sample memory cell;
adjust a second read level threshold of the memory cell to be centered between a third programming distribution and a fourth programming distribution before the second programming pass of the programming operation is performed on the second sample memory cell.

12. The system of claim 1 , wherein the memory cell, after the first programming pass, comprises the first programming distribution, the second programming distribution, a third programming distribution, and a fourth programming distribution, wherein the read level threshold is between the first programming distribution and the second programming distribution, a second read level threshold is between the second programming distribution and the third programming distribution, and a third read level threshold is between the third programming distribution and the fourth programming distribution.

13. The system of claim 1 , wherein the memory cell, after the second programming pass, comprises eight programming distributions and seven read level thresholds, each of the seven read level thresholds being set between two of the eight programming distributions.

14. The system of claim 1 , wherein:
the memory cell, after the first programming pass, comprises:
eight programming distributions including the first programming distribution and the second programming distribution; and
seven read level thresholds including the read level threshold, the memory cell, after the second programming pass, comprises:
sixteen programming distributions; and
fifteen read level thresholds, each of the fifteen read level thresholds being set between two of the sixteen programming distributions.

15. A method comprising:
determining that a first programming pass of a programming operation has been performed on a memory cell of a memory component; and
before a second programming pass of the programming operation is performed on the memory cell,
adjusting a read level threshold of the memory cell to be centered between a first programming distribution and a second programming distribution before the second programming pass of the programming operation is performed on the memory cell.

16. The method of claim 15 , further comprising performing the second programming pass of the programming operation on the memory cell.

17. The method of claim 15 , further comprising:
determining information about a valley between the first programming distribution and the second programming distribution before the second programming pass of the programming operation is performed on the memory cell.

18. The method of claim 15 , further comprising:
adjusting a second read level threshold of the memory cell to be centered between the second programming distribution and a third programming distribution before the second programming pass of the programming operation is performed on the memory cell.

19. A method comprising:
initiating a block programming sequence on a block of a memory component, the block programming sequence comprising at least a first programming pass and a second programming pass;
during block programming of a first sample page stack in the block, interrupting the block programming sequence before the second programming pass is performed;
while the block programming sequence is interrupted,
adjusting a read level threshold to be centered between two programming distributions of t

Assignees

• Micron Technology Inc

Inventors

• Sheperek Michael
• Koudele Larry J
• Liikanen Bruce A

Classifications

• G11C29/50004 Primary

  of threshold voltage · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• H04L1/203

  Details of error rate determination, e.g. BER, FER or WER · CPC title