Repair pixel and display apparatus having the same

Patent metadata

Field	Value
Publication number	US-11908377-B2
Application number	US-202217831442-A
Country	US
Kind code	B2
Filing date	Jun 3, 2022
Priority date	Aug 24, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A repair pixel and a display apparatus including the repair pixel, the display panel including a repair pixel for a pixel row or a plurality of repair pixels for a pixel row so that repair may be performed using the repair pixel when a bad pixel occurs in the corresponding pixel row. The bad pixel is repaired using the repair pixel so that the yield of the display panel may be enhanced.

First claim

What is claimed is:

1. A repair pixel comprising:
a first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node;
a second transistor including a control electrode configured to receive a write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to the first node;
a third transistor including a control electrode configured to receive a reference gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the first node;
a fourth transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the third node;
a fifth transistor including a control electrode configured to receive an emission signal, an input electrode configured to receive a first power voltage, and an output electrode connected to the second node;
a sixth transistor including a control electrode configured to receive the emission signal, an input electrode connected to the third node and an output electrode connected to a repair line; and
an initialization capacitor including a first electrode connected directly to the third node and a second electrode configured to receive the initialization voltage.

2. The repair pixel of claim 1 , further comprising a storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node.

3. The repair pixel of claim 2 , further comprising a hold capacitor including a first electrode configured to receive the first power voltage and a second electrode connected to the third node.

4. The repair pixel of claim 3 , wherein, in a first duration, the emission signal has an inactive level, the reference gate signal has an active level, the initialization gate signal has the active level, and the write gate signal has the inactive level.

5. The repair pixel of claim 4 , wherein, in a second duration subsequent to the first duration, the emission signal has the active level, the reference gate signal has the active level, the initialization gate signal has the inactive level and the write gate signal has the inactive level.

6. The repair pixel of claim 5 , wherein, in a third duration subsequent to the second duration, the emission signal has the inactive level, the reference gate signal has the inactive level, the initialization gate signal has the inactive level and the write gate signal has the active level.

7. The repair pixel of claim 6 ,
wherein when the reference voltage is VREF, a threshold voltage of the first transistor is VTH, the data voltage is VDATA, a capacitance of the storage capacitor is CST, a capacitance of the hold capacitor is CHOLD, a capacitance of the initialization capacitor is CI NT, and a voltage of the third node in the third duration is VS,

VS
=

(

VREF
-
VTH

)

+

CST

CST
+
CHOLD
+
CINT

⁢

(

VDATA
-
VREF

)

is satisfied.

8. The repair pixel of claim 6 , wherein, in a fourth duration subsequent to the third duration, the emission signal has the inactive level, the reference gate signal has the inactive level, the initialization gate signal has the active level, and the write gate signal has the inactive level.

9. The repair pixel of claim 6 , wherein, in a fifth duration subsequent to the third duration, the emission signal has the active level, the reference gate signal has the inactive level, the initialization gate signal has the inactive level, and the write gate signal has the inactive level.

10. The repair pixel of claim 9 ,
wherein, when the reference voltage is VREF, the data voltage is VDATA, a capacitance of the storage capacitor is CST, a capacitance of the hold capacitor is CHOLD, a capacitance of the initialization capacitor is CI NT, a mobility of the first transistor is μ, a capacitance per a unit area of the first transistor is C ox , a width to length ratio of the first transistor is W/L, and a source-drain current of the first transistor in the fifth duration is IDS,

IDS
=

1
2

⁢
uCox
⁢

W
L

⁢

(

CHOLD
+
CINT

CST
+
CHOLD
+
CINT

⁢

(

VDATA
-
VREF

)

)

2

is satisfied.

11. A repair pixel comprising:
a first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node;
a second transistor including a control electrode configured to receive a write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to the first node;
a third transistor including a control electrode configured to receive a reference gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the first node;
a fourth transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the third node;
a fifth transistor including a control electrode configured to receive an emission signal, an input electrode configured to receive a first power voltage, and an output electrode connected to the second node;
a sixth transistor including a control electrode configured to receive the emission signal, an input electrode connected to the third node and an output electrode connected to a repair line;
a storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node; and
a hold capacitor including a first electrode

Assignees

• Samsung Display Co Ltd

Inventors

• In Hai-Jung
• Son Sungmin
• Song Jae-Jin

Classifications

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title