Multi-processor bridge with cache allocate awareness

Patent metadata

Field	Value
Publication number	US-11907528-B2
Application number	US-202117380297-A
Country	US
Kind code	B2
Filing date	Jul 20, 2021
Priority date	Oct 15, 2018
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

First claim

What is claimed is:

1. A processing system comprising:
a plurality of processors including a first processor;
a cache memory coupled to the plurality of processors; and
a shared memory controller comprising:
circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
formatting circuitry configured to format the memory management command into a formatted command; and
routing circuitry configured to route the formatted command based on the specification; and
response circuitry configured to receive a response indicating the data was loaded into the memory location.

2. The processing system of claim 1 , wherein:
each of the plurality of processors shares the cache memory; and
the first processor and a second processor share the memory location of the cache memory.

3. The processing system of claim 1 , wherein:
the memory management command is a cache request.

4. The processing system of claim 1 , wherein:
the cache memory comprises an internal cache memory of the shared memory controller.

5. The processing system of claim 1 , wherein:
the routing circuitry is configured to route the formatted command to memory controller associated with the cache memory; and
the response circuitry is configured to receive the response from the memory controller.

6. The processing system of claim 1 , further comprising a badge circuit,
wherein a third processor of the plurality of processors is coupled to the cache memory by the bridge circuit.

7. The processing system of claim 6 , wherein:
the formatting circuitry is configured to format a second memory management command into a second formatted command configured for the bridge circuit;
the routing circuitry is configured to route the second formatted command to the bridge circuit;
the bridge circuit is configured to translate the second formatted command into an op code; and
the bridge circuit is configured to transmit the op code to a memory interface of the third processor.

8. The processing system of claim 1 , wherein:
the cache memory is an L2 cache memory.

9. The processing system of claim 1 , wherein:
the cache memory is an L3 cache memory; and
the response circuitry is configured to receive the response from the L3 cache memory.

10. A method comprising:
receiving, by a shared memory controller, a memory management command having a specification to perform a memory management operation to load data into a memory location of a cache memory before a first processor of a plurality of processors executes an input/output instruction that requests the data from the memory location;
formatting, by formatting circuitry, the memory management command into a formatted command;
routing, by routing circuitry, the formatted command based on the specification;
receiving, by response circuitry, a response indicating the data was loaded into the memory location.

11. The method of claim 10 , wherein:
each of the plurality of processors shares the cache memory; and
the first processor and a second processor of the plurality of processors share the memory location of the cache memory.

12. The method of claim 10 , wherein:
the memory management command is a cache request.

13. The method of claim 10 , wherein:
the cache memory comprises an internal cache memory of the shared memory controller.

14. The method of claim 10 , wherein:
routing the formatted command comprises the formatted command to a memory controller associated with the cache memory; and
receiving the response comprises receiving the response from the memory controller.

15. The method of claim 10 , wherein:
a third processor of the plurality of processors is coupled to the cache memory by a bridge circuit.

16. The method of claim 15 , further comprising:
formatting a second memory management command into a second formatted command configured for the bridge circuit;
routing the second formatted command to the bridge circuit;
translating, by the bridge circuit the second formatted command into an op code; and
transmitting, by the bridge circuit, the op code to a memory interface of the third processor.

17. The method of claim 10 , wherein:
the cache memory is an L2 cache memory.

18. The method of claim 10 , wherein:
the cache memory is an L3 cache memory; and
receiving the response comprises receiving the response from the L3 cache memory.

19. A processing system comprising:
a plurality of processors including a first processor and a second processor, wherein the second processor includes a memory interface;
a cache memory coupled to the plurality of processors;
a bridge circuit, wherein the second processor is coupled to the cache memory by the bridge circuit; and
a shared memory controller comprising:
circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
formatting circuitry configured to format the memory management command into a formatted command; and
routing circuitry configured to route the formatted command based on the specification to the bridge circuit; and
response circuitry configured to receive a first response from the bridge circuit,

wherein the bridge circuit is configured to:
translate the formatted command into an op code;
transmit the op code to the memory interface of the second processor;
receive a second response from the second processor indicating the data was loaded into the memory location; and
send the first response to the response circuitry indicating the data was loaded into the memory location.

20. The processing system of claim 19 ,
wherein the second response includes the data loaded into the memory location,
wherein the bridge circuit is configured to discard the data included in the second response, and
wherein the bridge circuit is configured to send the first response after receiving the second response.

Assignees

• Texas Instruments Inc

Inventors

• Chirca Kai
• Wu Daniel
• Pierson Matthew David

Classifications

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0607

  by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device · CPC title

• G06F3/0632

  by initialisation or re-initialisation of storage systems · CPC title