Backward compatibility testing of software in a mode that disrupts timing

Patent metadata

Field	Value
Publication number	US-11907105-B2
Application number	US-202117353675-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Nov 2, 2015
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A device having a Graphics Processing Unit (GPU) may be configured to selectively run in a normal mode or a timing testing mode. In the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and test the application for errors in device hardware component and/or software component synchronization while the device is running in the timing testing mode.

First claim

What is claimed is:

1. A device, comprising:
one or more processors including a graphics processing unit (GPU) and a central processing unit (CPU) core;
a memory coupled to the one or more processors; and
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors including the CPU core, wherein the operating system is configured to selectively run in a normal mode or a timing testing mode, wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and testing the application for errors in device hardware components synchronization and/or software components synchronization while the device is running in the timing testing mode, wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS replacing the firmware of GPU.

2. The device of claim 1 , wherein the OS modifies the frequency of at least one GPU subunit.

3. The device of claim 2 , wherein the OS continually modifies the frequency of at least one GPU subunit.

4. The device of claim 1 , wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS replacing the firmware of GPU with a firmware that has higher overhead for each object processed.

5. The device of claim 1 , wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS replacing the firmware of GPU with a firmware that supports a lower count of objects that can be processed simultaneously than the normal firmware.

6. The device of claim 1 , wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes reducing a size of a GPU cache.

7. The device of claim 1 , wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes reducing a rate of execution of all instructions or specific instructions running on the GPU.

8. The device of claim 1 , wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS requesting the GPU to perform other processing tasks that reduce the remaining resources available to the application.

9. The device of claim 8 , wherein the OS requests the GPU to perform the other processing tasks at random times while running the application.

10. The device of claim 8 , wherein the OS requests the GPU to perform rendering of graphical objects or compute shaders at a higher priority than the application while running the application.

11. The device of claim 8 , wherein the OS requests the GPU to process the application on specific cores.

12. The device of claim 1 , wherein the disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS requesting the GPU to write back or invalidate GPU caches.

13. The device of claim 1 , wherein the disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS requesting the GPU to writeback or invalidate GPU Instruction Translation Lookaside Buffers (ITLBs).

14. The device of claim 1 , wherein the disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS requesting the GPU to write back or invalidate GPU Data Translation Lookaside Buffers (DTLBs).

15. A device, comprising:
one or more processors including a graphics processing unit (GPU) and a central processing unit (CPU) core;
a memory coupled to the one or more processors; and
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors including the CPU core, wherein the operating system is configured to selectively run in a normal mode or a timing testing mode, wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and testing the application for errors in device hardware components synchronization and/or software components synchronization while the device is running in the timing testing mode, wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU changing the GPU caching behavior and GPU cache lookup behavior from being based on a virtual address to being based on a physical address.

16. A device, comprising:
one or more processors including a graphics processing unit (GPU) and a central processing unit (CPU) core;
a memory coupled to the one or more processors; and
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors including the CPU core, wherein the operating system is configured to selectively run in a normal mode or a timing testing mode, wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and testing the application for errors in device hardware components synchronization and/or software components synchronization while the device is running in the timing testing mode, wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes changing the GPU caching behavior and GPU cache lookup behavior from being based on a physical address to being based on a virtual address.

17. A device, comprising:
a Graphics Processing Unit (GPU);
a Central Processing Unit (CPU) Core;
an operating system (OS) configured to run on at least a subset of the one or more processors including the CPU core, wherein the device is configured to selectively run in a normal mode or a timing testing mode with the CPU core, wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and testing the application for errors in device hardware component synchronization and/or software component synchronization while the device is running in the timing testing mode, wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS replacing firmware of the GPU.

18. A non-transitory computer readable medium having computer readable executable instructions embodied therein, the instructions being configured to cause a device having a Graphics Processing Unit (GPU) to implement a method upon execution of the instructions, the method comprising:
running the device in a timing testing mode with a Central Processing Unit (CPU) core, wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU; and
testing the application for errors in device hardware component synchronization and/or software component synchronization while the device is running in the timing testing mode, wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes an operating system (OS) replacing firmware of the GPU.

Assignees

• Sony Interactive Entertainment LLC

Inventors

• Cerny Mark Evan
• Simpson David

Classifications

• G06F11/3668 Primary

  Testing of software · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30079

  Pipeline control instructions, e.g. multicycle NOP · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• G06F11/3684 Primary

  for test design, e.g. generating new test cases · CPC title