Adaptive wake-up for power conservation in a processor

Patent metadata

Field	Value
Publication number	US-11907043-B2
Application number	US-202217664999-A
Country	US
Kind code	B2
Filing date	May 25, 2022
Priority date	May 25, 2022
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing pipelines associated with different tasks, the plurality of processing pipelines including:
a first pipeline having a first memory circuit and a first logic circuit configured to process a physical downlink control channel;
a second pipeline having a second memory circuit and a second logic circuit configured to process a downlink data channel; and
a third pipeline having a third memory circuit and a third logic circuit configured to process one or more uplink data channels; and

a power management circuit configured to determine when to supply power to the first, second, and third memory circuits and the first, second, and third logic circuits, wherein the power management circuit is configured to:
periodically power up the first memory circuit and the first logic circuit to enable a listening operation to detect a data communication request;
power up the second and third memory circuits and the second and third logic circuits when data communication is requested; and
transition the second and third memory circuits and the second and third logic circuits to a lower power state in response to determining that data communication has ended.

2. The processor of claim 1 wherein the power management circuit is further configured such that the listening operation includes listening for a paging signal indicating that a base station has data to send to the processor.

3. The processor of claim 1 wherein the power management circuit is further configured to determine that data communication is requested based at least in part on an interrupt signal from a different processor indicating that the different processor has data ready to be transmitted.

4. The processor of claim 1 wherein the power management circuit is further configured such that determining that data communication has ended includes determining whether the processor has entered a connected discontinuous receive (CDRX) state or an idle state.

5. The processor of claim 1 wherein the plurality of processing pipelines includes a plurality of instances of the second pipeline having one or more instances of the second memory circuit and the second logic circuit and wherein the power management circuit is further configured to:
determine a type of data communication requested; and
power up the one or more instances of the second memory circuit and the second logic circuit based at least in part on the type of data communication.

6. The processor of claim 1 wherein the first, second, and third memory circuits are volatile memory circuits and wherein the power management circuit is further configured such that transitioning one or more of the first, second, or third memory circuits to the lower power state includes saving data from the first, second, or third memory circuit to a different memory circuit that is not transitioning to the lower power state.

7. The processor of claim 6 wherein the power management circuit is further configured such that powering up one or more of the first, second, or third memory circuits includes restoring data from the different memory circuit to the first, second, or third memory circuit.

8. An electronic device comprising:
a first processor; and
a second processor coupled to the first processor,
wherein the second processor includes:
a plurality of processing pipelines associated with different tasks, the plurality of processing pipelines including:
a first pipeline having a first memory circuit and a first logic circuit configured to process a physical downlink control channel;
a second pipeline having a second memory circuit and a second logic circuit configured to process a physical downlink shared channel; and
a third pipeline having a third memory circuit and a third logic circuit configured to process one or more physical uplink channels; and

a power management circuit configured to manage one or more power states, including:
a sleep state in which the first, second, and third memory circuits and the first, second, and third logic circuits are in a low power state;
a listening state in which the first memory circuit and the first logic circuit are powered up while the second and third memory circuits and the second and third logic circuits are in the low power state; and
a data communication state in which the first, second, and third memory circuits and the first, second, and third logic circuits are powered up, wherein the power management circuit is further configured to:

periodically transition from the sleep state to the listening state;
while in the listening state, determine whether data communication should be enabled and transition from the listening state to the data communication state in response to determining that data communication should be enabled; and
while in the data communication state, determine data communication has ended and transition from the data communication state to the sleep state in response to determining that data communication has ended.

9. The electronic device of claim 8 wherein the power management circuit is further configured to:
receive an interrupt signal from the first processor while in either the sleep state or the listening state, the interrupt signal indicating that the electronic device has data ready to be sent; and
transition to the data communication state in response to receiving the interrupt signal.

10. The electronic device of claim 8 wherein the plurality of processing pipelines includes a plurality of instances of the second pipeline and wherein the one or more power states include a plurality of data communication states including:
a first data communication state in which all instances of the second pipeline are powered up; and
a second data communication state in which at least one and fewer than all instances of the second pipeline are powered up,
wherein the power management circuit is further configured to select one of the plurality of data communication states based on a type of data communication that should be enabled.

11. The electronic device of claim 10 wherein the second processor comprises a cellular modem processor configured to support data communication using a 4G radio area network and data communication using a 5G radio area network, and wherein the power management circuit is further configured to select the first data communication state for data communication using the 5G radio area network and to select the second data communication state for data communication using the 4G radio area network.

12. The electronic device of claim 8 wherein the first, second, and third memory circuits are volatile memory circuits and wherein the power management circuit is further configured such that powering down one or more of the first, second, or third memory circuits includes saving data from the first, second, or third memory circuit to a different memory circuit that is not being powered down.

13. The electronic device of claim 12 wherein the power management circuit is further configured such that powering up one or more of the first, second, or third memory circuits includes restoring data from the different memory circuit to the first, second, or third memory circuit.

14. A method implemented in a processor, the method comprising:
placing the processor into a sleep state in which a plurality of processing pipelines are in a low power state, wherein the plurality of processing pipelines includes a first pipeline having a first memory circuit and a first logic circuit configured to process a physical downlink control channel, a second pipeline having a second memo

Assignees

• Apple Inc

Inventors

• Zhou Ping
• Schlegel Nikolai
• Ehsan Navid
• Chen Zhimin
• Jennings Gerard D

Classifications

• Y02D30/70

  in wireless communication networks · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3209

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title

• G06F1/3278

  Power saving in modem or I/O interface · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title