Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Patent metadata

Field	Value
Publication number	US-10509576-B2
Application number	US-201715786424-A
Country	US
Kind code	B2
Filing date	Oct 17, 2017
Priority date	Dec 22, 2011
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

First claim

What is claimed is:

1. A system comprising:
a central processing unit (CPU);
a device external to the CPU and comprising software registers to be operated on by a device driver and hardware registers to store a context;
a power control unit to control transitions into a deep power down state;
a static memory to store the context when the device is in the deep power down state; and
a sustain power well to provide a reduced voltage during the deep power down state to allow the static memory to maintain integrity of context data stored therein, but is less than enough to allow the device to remain in idle state, the sustain power well further to allow the power control unit to monitor read or write commands from the device driver to the software registers and wake the device in response.

2. The system of claim 1 , wherein the power control unit is to monitor a status of the device, including the operations on the software registers, and, when the device is idle, to cause the context to be stored in the static memory, and then place the device into the deep power down state.

3. The system of claim 2 , wherein, when the device is in the deep power down state, the power control unit, in response to a monitored event, is to wake the device, cause the context to be loaded from the static memory into the device, place the device into an active state, and cause an active device voltage and an active memory voltage to be provided to the device and to the static memory, respectively.

4. The system of claim 1 , wherein the power control unit is to monitor the operations on the software, power control operations performed on the device, transactions between the device and one or more other devices, and transactions between the device and the CPU.

5. The system of claim 1 , wherein the power control unit is to place the device into the deep power down state in lockstep with the CPU.

6. The system of claim 1 , wherein the power control unit is to place the device into the deep power down state independently from, and regardless of an activity level of, the CPU.

7. The system of claim 1 , wherein the device consumes less power when in the deep power down state than in an idle state.

8. A method performed by a system comprising a central processing unit (CPU) and a device external to the CPU and comprising software registers to be operated on by a device driver and hardware registers to store a context, the method comprising:
monitoring the device, by a power control unit, and determining that the device should be placed into a deep power down state;
copying the context to a static memory and placing the device into the deep power down state; and
providing, using a sustain power well, a nominal voltage level to the device and the static memory during the deep power down state, the nominal voltage level being sufficient to allow the static memory to maintain integrity of context data stored therein, but being less than enough to allow the device to remain in idle state, the sustain power well further to allow the power control unit to monitor read or write commands from the device driver to the software registers and wake the device in response.

9. The method of claim 8 , wherein, when the device is in the deep power down state, the power control unit, in response to a monitored event, is to wake the device, cause the context to be loaded from the static memory into the device, place the device into an active state, and cause an active device voltage and an active memory voltage to be provided to the device and to the static memory, respectively.

10. The method of claim 8 , wherein the power control unit is to monitor operations by the device driver on the software registers, power control operations performed on the device, transactions between the device and one or more other devices, and transactions between the device and the CPU.

11. The method of claim 8 , wherein the power control unit is to place the device into the deep power down state in lockstep with the CPU.

12. The method of claim 8 , wherein the power control unit is to place the device into the deep power down state independently from, and regardless of an activity level of, the CPU.

13. The method of claim 8 , wherein the device consumes less power when in the deep power down state than in an idle state.

14. A processor comprising:
a processing core;
a device external to the processing core and comprising software registers to be operated on by a device driver and hardware registers to store a context;
a static memory to store the context when the device is in a deep power down state;
a power control unit to place the device into the deep power down state; and
a sustain power well to provide a reduced voltage during the deep power down state to allow the static memory to maintain integrity of context data stored therein, the reduced voltage being less than enough to allow device to remain in idle state, the sustain power well further to allow the power control unit to monitor read or write commands from the device driver to the software registers and wake the device in response.

15. The processor of claim 14 , wherein the power control unit is to monitor a status of the device, including operations on the software registers, and, when the device is idle, to cause the context to be stored in the static memory, and then place the device into the deep power down state.

16. The processor of claim 14 , wherein, when the device is in the deep power down state, the power control unit, in response to a monitored event, is to wake the device, cause the context to be loaded from the static memory into the device, place the device into an active state, and cause an active device voltage and an active memory voltage to be provided to the device and to the static memory, respectively.

17. The processor of claim 14 , wherein the power control unit is to monitor operations by the device driver on the software registers, power control operations performed on the device, transactions between the device and one or more other devices, and transactions between the device and the processing core.

18. The processor of claim 14 , wherein the power control unit is to place the device into the deep power down state in lockstep with the processing core.

19. The processor of claim 14 , wherein the power control unit is to place the device into the deep power down state independently from, and regardless of an activity level of, the processing core.

20. The processor of claim 14 , wherein the device consumes less power when in the deep power down state than in an idle state.

Assignees

• Intel Corp

Inventors

• Sodhi Inder M
• Naveh Alon
• Rajwan Doron
• Wells Ryan D
• Samson Eric C

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G06F1/3278

  Power saving in modem or I/O interface · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title