Method and apparatus improving gate oxide reliability by controlling accumulated charge

Patent metadata

Field	Value
Publication number	US-11901459-B2
Application number	US-202117549839-A
Country	US
Kind code	B2
Filing date	Dec 13, 2021
Priority date	Jul 11, 2005
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A method and apparatus are disclosed for use in improving gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit includes a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

First claim

What is claimed is:

1. A switch comprising:
a first port;
a second port;
a third port;
a first switch circuit configured to selectively couple a signal received at the first port to the second port based on a first switch control signal; and
a second switch circuit configured to selectively couple the signal received at the first port to the third port based on a second switch control signal, wherein the second switch circuit comprises an accumulated charge sink (ACS) and a transistor comprising a source, a drain, a gate, and a body coupled to the ACS, and wherein the ACS is configured to receive a bias voltage during at least a portion of a duration when the second switch circuit is configured to not couple the signal received at the first port to the third port to prevent charge from accumulating in the body,
wherein the switch is configured to:
pass the signal received at the first port to the second port via the first switch circuit when the first switch circuit is in an on state and the second switch circuit is in an off state; and
pass the signal received at the first port to the third port via the second switch circuit when the first switch circuit is in an off state and the second switch circuit is in an on state.

2. The switch of claim 1 , wherein the gate is coupled to the ACS, and wherein the charge is associated with carriers having a polarity opposite a polarity of carriers associated with the source and the drain.

3. The switch of claim 1 , wherein the bias voltage is equal to or more negative than a bias voltage applied to the source and a bias voltage applied to the drain.

4. The switch of claim 1 , wherein, during the portion of the duration, the transistor is configured to be electrically biased to have a voltage level substantially more negative than a lowest voltage level of the following: ground, a voltage level associated with the source of the transistor, and a voltage level associated with the drain of the transistor.

5. The switch of claim 1 , wherein the transistor further comprises a gate oxide having a thickness less than approximately 8.2 nm.

6. The switch of claim 1 , further comprising a semiconductor-on-insulator substrate, and wherein the first switch circuit and the second switch circuit are formed in a layer of semiconductor material.

7. The switch of claim 6 , wherein the layer has a thickness between approximately 100 angstroms to approximately 2,000 angstroms.

8. The switch of claim 1 , wherein the third port is connected to ground.

9. The switch of claim 1 , wherein the first switch circuit comprises a plurality of transistors coupled together in a stacked configuration.

10. The switch of claim 1 , wherein the second switch circuit further comprises at least one additional transistor, and wherein the transistor and the at least one additional transistor are coupled together in a stacked configuration.

11. The switch of claim 1 , wherein the second switch circuit further comprises a diode coupled between the gate and the ACS.

12. The switch of claim 11 , wherein the diode is configured to prevent current flow into the body when the transistor is in an on state.

13. The switch of claim 11 , wherein the second switch circuit further comprises a capacitor in parallel with the diode.

14. The switch of claim 9 , wherein the first switch circuit is configured to selectively couple the signal received at the first port to the second port via the plurality of transistors.

15. A method comprising:
selectively coupling, by a first switch circuit, a signal received at a first port to a second port based on a first switch control signal, wherein the selectively coupling by the first switch circuit comprises passing the signal received at the first port to the second port via the first switch circuit when the first switch circuit is in an on state and a second switch circuit is in an off state;
selectively coupling, by a transistor of the second switch circuit, the signal received at the first port to a third port based on a second switch control signal, wherein the selectively coupling by the transistor of the second switch circuit comprises passing the signal received at the first port to the third port via the second switch circuit when the first switch circuit is in an off state and the second switch circuit is in an on state; and
receiving, by an accumulated charge sink (ACS) of the second switch circuit, a bias voltage during at least a portion of a duration when the second switch circuit does not couple the signal received at the first port to the third port to prevent charge from accumulating in a transistor body of the second switch circuit.

16. The method of claim 15 , wherein the bias voltage is equal to or more negative than a bias voltage applied to a transistor source of the second switch circuit and a bias voltage applied to a transistor drain of the second switch circuit.

17. The method of claim 15 , wherein, during the portion of the duration, the transistor is electrically biased to have a voltage level substantially more negative than a lowest voltage level of the following: ground, a voltage level associated with a transistor source, and a voltage level associated with a transistor drain.

18. The method of claim 15 , wherein the charge is associated with carriers having a polarity opposite a polarity of carriers associated with a transistor source of the second switch circuit and a transistor drain of the second switch circuit.

19. The method of claim 15 , further comprising preventing, by a diode coupled between a gate of the transistor and the ACS of the second switch circuit, current flow into the transistor body when the transistor is in an on state.

20. The method of claim 15 , wherein the second switch circuit further comprises at least one additional transistor, and wherein the selectively coupling by the transistor comprises selectively coupling the signal received at the first port to the third port via the transistor and the at least one additional transistor.

Assignees

• Psemi Corp

Inventors

• Stuber Michael A
• Brindle Christopher N
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George P
• Welstand Robert B
• Burgener Mark L
• Dribinsky Alexander
• Kim Tae-Youn

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D30/6759

  Silicon-on-sapphire [SOS] substrates · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title