Array substrate and method of manufacturing the same, and display apparatus

Patent metadata

Field	Value
Publication number	US-11901367-B2
Application number	US-202117788024-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Jun 19, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A method of manufacturing an array substrate, includes: providing a substrate; forming a gate conductive layer including at least one first alignment mark; forming a source-drain conductive thin film; aligning a first mask and the substrate on which the gate conductive layer and the source-drain conductive thin film have been formed according to the at least one first alignment mark; patterning the source-drain conductive thin film by using the first mask to form at least one second alignment mark to obtain a source-drain conductive layer; forming a black matrix thin film; aligning a second mask and the substrate on which the gate conductive layer, the source-drain conductive layer and the black matrix thin film have been formed according to the at least one second alignment mark; patterning the black matrix thin film by using the second mask to form a black matrix; and forming a color filter layer.

First claim

What is claimed is:

1. A method of manufacturing an array substrate, the method comprising:
providing a substrate, the substrate having a display area and a bezel area;
forming a gate conductive layer on a side of the substrate, the gate conductive layer including gates of a plurality of thin film transistors and at least one first alignment mark located in the bezel area;
forming a source-drain conductive thin film on a side of the gate conductive layer away from the substrate;
aligning a first mask and the substrate on which the gate conductive layer and the source-drain conductive thin film have been formed according to the at least one first alignment mark;
patterning the source-drain conductive thin film by using the first mask as a shield to form sources and drains of the plurality of thin film transistors and at least one second alignment mark located in the bezel area, so as to obtain a source-drain conductive layer, wherein a reflectivity of the source-drain conductive layer is greater than a reflectivity of the gate conductive layer;
forming a black matrix thin film on a side of the source-drain conductive layer away from the substrate;
aligning a second mask and the substrate on which the gate conductive layer, the source-drain conductive layer and the black matrix thin film have been formed according to the at least one second alignment mark;
patterning the black matrix thin film by using the second mask as a shield to form a black matrix, wherein orthographic projections of the plurality of thin film transistors on the substrate are located within an orthographic projection of the black matrix on the substrate; and
forming a color filter layer on the substrate on which the black matrix has been formed.

2. The method of manufacturing the array substrate according to claim 1 , wherein the source-drain conductive thin film includes a first titanium thin film, an aluminium thin film and a second titanium thin film that are sequentially stacked.

3. The method of manufacturing the array substrate according to claim 1 , wherein a material of the gate conductive layer includes molybdenum.

4. The method of manufacturing the array substrate according to claim 1 , wherein the color filter layer includes color filter portions of a plurality of colors; and
forming the color filter layer, includes: sequentially forming color filter portions of each of the plurality of colors.

5. The method of manufacturing the array substrate according to claim 4 , wherein forming color filter portions of a single color, includes:
forming a color filter thin film of the single color on the substrate on which the black matrix has been formed;
aligning a third mask and the substrate on which the gate conductive layer, the source-drain conductive layer, the black matrix and the color filter thin film have been formed according to the at least one second alignment mark; and
patterning the color filter thin film by using the third mask as a shield to form the color filter portions of the single color.

6. The method of manufacturing the array substrate according to claim 1 , the method further comprising:
forming a first electrode thin film on a side of the color filter layer away from the substrate;
aligning a fourth mask and the substrate on which the gate conductive layer, the source-drain conductive layer, the black matrix, the color filter layer and the first electrode thin film have been formed according to the at least one second alignment mark;
patterning the first electrode thin film by using the fourth mask as a shield to form a first electrode layer;
forming a second electrode thin film on a side of the first electrode layer away from the substrate;
aligning a fifth mask and the substrate on which the gate conductive layer, the source-drain conductive layer, the black matrix, the color filter layer, the first electrode layer and the second electrode thin film have been formed according to the at least one second alignment mark; and
patterning the second electrode thin film by using the fifth mask as a shield to form a second electrode layer;
wherein the sources or the drains of the plurality of thin film transistors are electrically connected to respective electrodes of the first electrode layer.

7. The method of manufacturing the array substrate according to claim 1 , wherein the source-drain conductive thin film includes a silver thin film.

8. The method of manufacturing the array substrate according to claim 1 , the method further comprising:
forming a first electrode thin film on a side of the color filter layer away from the substrate;
aligning a fourth mask and the substrate on which the gate conductive layer, the source-drain conductive layer, the black matrix, the color filter layer and the first electrode thin film have been formed according to the at least one second alignment mark;
patterning the first electrode thin film by using the fourth mask as a shield to form a first electrode layer;
forming a second electrode thin film on a side of the first electrode layer away from the substrate;
aligning a fifth mask and the substrate on which the gate conductive layer, the source-drain conductive layer, the black matrix, the color filter layer, the first electrode layer and the second electrode thin film have been formed according to the at least one second alignment mark; and
patterning the second electrode thin film by using the fifth mask as a shield to form a second electrode layer;
wherein the sources or the drains of the plurality of thin film transistors are electrically connected to respective electrodes of the second electrode layer.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Yan
• Chen Yanqing
• Li Wei
• Wang Ning
• Qin Weida
• Zhang Zhao
• Li Jing
• Yang Feng

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title