Discontinuous patterned bonds for semiconductor devices and associated systems and methods

US11901342B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11901342-B2
Application numberUS-202217570973-A
CountryUS
Kind codeB2
Filing dateJan 7, 2022
Priority dateAug 29, 2011
Publication dateFeb 13, 2024
Grant dateFeb 13, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

First claim

Opening claim text (preview).

We claim: 1. A semiconductor device, comprising: a substrate having a first surface and a second surface opposite the first surface, wherein the second surface includes a recess completely surrounded by a peripheral region of the second surface; a first layer of bonding material disposed in direct contact with a bottom surface of the recess; a second layer of bonding material directly bonded to the first layer of bonding material and disposed entirely within the recess; and a solid state transducer directly bonded to the second layer of bonding material and disposed within the recess, wherein the substrate comprises silicon, polycrystalline aluminum nitride, or sapphire. 2. The semiconductor device of claim 1 , wherein the solid state transducer has an upper surface coplanar with the second surface. 3. The semiconductor device of claim 1 , wherein the recess has a depth from the second surface to the bottom surface of between about 5 microns and about 15 microns. 4. The semiconductor device of claim 1 , wherein the first bonding material and the second bonding material comprise copper, aluminum, gold, tin, nickel, palladium, indium, and/or an alloy thereof. 5. The semiconductor device of claim 1 , wherein the first bonding material and the second bonding material have different material compositions. 6. The semiconductor device of claim 1 , wherein the first layer of bonding material completely covers the bottom surface of the recess. 7. The semiconductor device of claim 1 , wherein the second layer of bonding material does not completely cover the first layer of bonding material. 8. The semiconductor device of claim 1 , wherein the solid state transducer has a same footprint as the second layer of bonding material. 9. The semiconductor device of claim 1 , wherein the solid state transducer and the second layer of bonding material are laterally spaced apart from interior sidewalls of the recess. 10. A semiconductor device, comprising: a silicon substrate having a front surface and a back surface opposite the front surface, wherein the front surface includes a recess defined by a bottom surface situated between the front surface and the back surface and by sidewalls surrounding the recess; a first layer of bonding material disposed in direct contact with a bottom surface of the recess and with the sidewalls; a second layer of bonding material directly bonded to the first layer of bonding material and spaced laterally apart from one or more of the sidewalls; and a solid state transducer directly bonded to the second layer of bonding material spaced laterally apart from one or more of the sidewalls. 11. The semiconductor device of claim 10 , wherein the solid state transducer has an upper surface coplanar with the front surface. 12. The semiconductor device of claim 10 , wherein the first bonding material and the second bonding material comprise copper, aluminum, gold, tin, nickel, palladium, indium, and/or an alloy thereof. 13. The semiconductor device of claim 10 , wherein the substrate comprises silicon, polycrystalline aluminum nitride, or sapphire. 14. The semiconductor device of claim 10 , wherein the first layer of bonding material completely covers the bottom surface of the recess. 15. The semiconductor device of claim 10 , wherein the second layer of bonding material has a different footprint than the first layer of bonding material. 16. The semiconductor device of claim 10 , wherein the solid state transducer has a same footprint as the second layer of bonding material. 17. A semiconductor device, comprising: a silicon substrate having a front surface and a back surface opposite the front surface, wherein the front surface includes a recess defined by a bottom surface situated between the front surface and the back surface and by sidewalls surrounding the recess; a first layer of bonding material disposed in direct contact with a bottom surface of the recess and with the sidewalls; a second layer of bonding material directly bonded to the first layer of bonding material and not in contact with any of the sidewalls; and a solid state transducer directly bonded to the second layer of bonding material and not in contact with any of the sidewalls. 18. The semiconductor device of claim 17 , wherein the solid state transducer has an upper surface coplanar with the front surface. 19. The semiconductor device of claim 17 , wherein the first bonding material and the second bonding material comprise copper, aluminum, gold, tin, nickel, palladium, indium, and/or an alloy thereof.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • of die-attach connectors · CPC title

  • involving guiding structures, e.g. spacers or supporting members · CPC title

  • Active alignment, e.g. using optical alignment using marks or sensors · CPC title

  • the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title

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What does patent US11901342B2 cover?
Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bo…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 13 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).