Diffusion layers in metal interconnects

US11901225B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11901225-B2
Application numberUS-202117474394-A
CountryUS
Kind codeB2
Filing dateSep 14, 2021
Priority dateSep 14, 2021
Publication dateFeb 13, 2024
Grant dateFeb 13, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Exemplary methods of plating are described. The methods may include contacting a patterned substrate with a plating bath in a plating chamber. The patterned substrate includes at least one metal interconnect with a contact surface that is exposed to the plating bath. The metal interconnect is made of a first metal characterized by a first reduction potential. The methods further include plating a diffusion layer on the contact surface of the metal interconnect. The diffusion layer is made of a second metal characterized by a second reduction potential that is larger than the first reduction potential of the first metal in the metal interconnects. The plating bath also includes one or more ions of the second metal and a grain refining compound that reduces the formation of pinhole defects in the diffusion layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A plating method comprising: contacting a patterned substrate with a plating bath in a plating chamber, wherein the pattern substrate comprises at least one metal interconnect with a contact surface that is exposed to the plating bath, and wherein the metal interconnect is made of a first metal characterized by a first reduction potential; and plating a diffusion layer on the contact surface of the metal interconnect, wherein the diffusion layer is made of a second metal characterized by a second reduction potential that is larger than the first reduction potential of the first metal in the at least one metal interconnect, wherein the plating bath comprises one or more ions of the second metal and a grain refining compound that reduces the formation of pinhole defects in the diffusion layer, the grain refining compound is characterized by a concentration in the plating bath of less than or about 0.05 M, and wherein the diffusion layer is plated on the contact surface of the metal interconnect at a rate of less than or about 5 nm/min. 2. The plating method of claim 1 , wherein the first metal in the at least one metal interconnect is copper. 3. The plating method of claim 1 , wherein the second metal in the diffusion layer is selected from the group consisting of silver, gold, platinum, palladium, and germanium. 4. The plating method of claim 1 , wherein the grain refining compound comprises glyoxylic acid or ethylene diamine tetraacetic acid. 5. The plating method of claim 1 , wherein the plating bath further comprises at least one stabilizer compound comprising imidazole or succinimide. 6. The plating method of claim 1 , wherein the diffusion layer is plated on the contact surface of the metal interconnect by electroless plating. 7. The plating method of claim 1 , wherein the plating bath is characterized by a temperature of less than or about 25° C. during the plating of the diffusion layer. 8. The plating method of claim 1 , wherein the plating bath is characterized by a temperature of less than or about 5° C. during the plating of the diffusion layer. 9. The plating method of claim 1 , wherein the plating bath is characterized by a concentration of one or more ions of the second metal that is less than or about 0.01 M. 10. A plating method comprising: contacting a patterned substrate with a plating bath in a plating chamber, the pattern substrate comprises at least one copper interconnect with a contact surface that is exposed to the plating bath; and plating a diffusion layer on the contact surface of the copper interconnect, wherein the diffusion layer is made of silver, and wherein the plating bath is characterized by a temperature of less than or about 5° C. during the plating of the diffusion layer, and wherein the plating bath is characterized by a concentration of silver ions that is less than or about 0.01 M. 11. The plating method of claim 10 , wherein the diffusion layer is plated on the contact surface of the copper interconnect at a rate of less than or about 1 nm/min. 12. The plating method of claim 10 , wherein the diffusion layer is characterized by a thickness of less than or about 10 nm, and wherein the diffusion layer is free of pinhole defects. 13. The plating method of claim 10 , wherein the plating bath further comprises a grain refining compound selected from the group consisting of glyoxylic acid and ethylene diamine tetraacetic acid. 14. The plating method of claim 10 , wherein the plating bath further comprises at least one stabilizer compound comprising imidazole or succinimide.

Assignees

Inventors

Classifications

  • Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

  • by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

  • the principal metal being copper · CPC title

  • by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition · CPC title

  • Subject matter not provided for in other groups of this subclass · CPC title

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What does patent US11901225B2 cover?
Exemplary methods of plating are described. The methods may include contacting a patterned substrate with a plating bath in a plating chamber. The patterned substrate includes at least one metal interconnect with a contact surface that is exposed to the plating bath. The metal interconnect is made of a first metal characterized by a first reduction potential. The methods further include plating…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/044. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 13 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).