Non-volatile memory device and method for programming the same using multiple program operations under different conditions

Patent metadata

Field	Value
Publication number	US-11901021-B2
Application number	US-202117530586-A
Country	US
Kind code	B2
Filing date	Nov 19, 2021
Priority date	Nov 19, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

First claim

What is claimed is:

1. A method for programming a non-volatile memory device, the method comprising:
determining a first condition comprising at least one of a first voltage level and a first application time;
performing a first program operation by providing at least one voltage to at least one of a word line and a bit line according to the first condition;
determining a second condition comprising at least one of a second voltage level and a second application time based on a result of the first program operation, wherein the second voltage level is different from the first voltage level and the second application time is different from the first application time; and
performing a second program operation by providing the at least one voltage to at least one of the word line and the bit line according to the second condition,
wherein the non-volatile memory device includes:
a substrate;
a memory cell region including a first metal pad and a plurality of memory cells formed perpendicularly to the substrate, wherein the plurality of memory cells are connected to a plurality of word lines comprising the word line and to a plurality of bit lines comprising the bit line; and
a peripheral region including a second metal pad and a voltage generator configured to generate the at least one voltage, wherein the peripheral region is connected to the plurality of memory cells through the first metal pad and the second metal pad.

2. The method of claim 1 , wherein the at least one voltage comprises a program voltage, the word line comprises a selected word line connected to a selected memory cell of the plurality of memory cells, and the first program operation and the second program operation comprise providing the program voltage to the selected word line according to the first condition and the second condition, respectively.

3. The method of claim 2 , wherein the at least one voltage further comprises an adjacent voltage, and the first program operation and the second program operation further comprise providing the adjacent voltage to an adjacent word line of the plurality of word lines, wherein the adjacent word line is immediately adjacent to the selected word line, according to the first condition and the second condition, respectively.

4. The method of claim 2 , wherein the at least one voltage further comprises a pass voltage, and the first program operation and the second program operation further comprise providing the pass voltage to a non-adjacent word line of the plurality of word lines, wherein the non-adjacent word line is not immediately adjacent to the selected word line, according to the first and second condition, respectively.

5. The method of claim 1 , wherein the at least one voltage comprises a bit line voltage, the bit line comprises a selected bit line connected to a selected memory cell of the plurality of memory cells, and the first program operation and the second program operation comprise providing the bit line voltage to the selected bit line according to the first condition and the second condition, respectively.

6. The method of claim 1 , wherein the at least one voltage comprises a program voltage, a string select line voltage and a ground select line voltage, wherein the word line comprises a selected word line connected to a selected memory cell of the plurality of memory cells, and wherein the first program operation and the second program operation comprise providing the program voltage to the selected word line, providing the string select line voltage to a string select line connected to the selected memory cell, and providing the ground select line voltage to a ground select line connected to the selected memory cell, according to the first and second condition, respectively.

7. The method of claim 1 , wherein the second voltage level is higher than the first voltage level.

8. The method of claim 1 , wherein the first condition further comprises at least one of at least one third voltage level and a third application time, and the second condition further comprises at least one of at least one fourth voltage level and a fourth application time, the method further comprising:
performing a first verify operation after the first program operation by providing a verify voltage to the word line according to the first condition; and
performing a second verify operation after the second program operation by providing the verify voltage to the word line according to the second condition.

9. The method of claim 8 , wherein the at least one third voltage level comprises a first plurality of voltage levels and the at least one fourth voltage level comprises a second plurality of voltage levels, the method further comprising:
providing the verify voltage to the word line at the first plurality of voltage levels during the first verify operation; and
providing the verify voltage to the word line at the second plurality of voltage levels during the second verify operation,
wherein a voltage level of the second plurality of voltage levels is higher than a voltage level of the first plurality of voltage levels,
wherein voltage levels of each of the first plurality of voltage levels and the second plurality of voltage levels decrease as time increases during the first verify operation and the second program operation, respectively, and
wherein the voltage levels of the first plurality of voltage levels decrease at a different rate than the voltage levels of the second plurality of voltage levels.

10. The method of claim 1 , wherein the second voltage level is lower than the first voltage level.

11. The method of claim 1 , wherein the bit line is connected to a memory cell to be verified, the method further comprising:
providing the at least one voltage to the plurality of bit lines according to the first condition; and
providing the at least one voltage to the bit line according to the second condition.

12. A method for programming at least one selected memory cell of a plurality of memory cells included in a non-volatile memory device, each of the plurality of memory cells being connected to a word line of a plurality of word lines and a bit line of a plurality of bit lines, the non-volatile memory device including a memory cell region including a first metal pad and the plurality of memory cells, the non-volatile memory device further including a peripheral region including a second metal pad and a voltage generator the peripheral region connected to the plurality of memory cells through the first metal pad and the second metal pad, the method comprising:
performing a first program operation based on a first condition, the first program operation including:
generating a first bit line voltage, a first program voltage, a first adjacent voltage, and a first pass voltage by the voltage generator, wherein voltage levels and voltage application times of the first bit line voltage, the first program voltage, the first adjacent voltage, and the first pass voltage correspond to the first condition; and
providing the first bit line voltage to a selected bit line connected to the at least one selected memory cell, providing the first program voltage to a selected word line connected to the at least one selected memory cell, providing the first adjacent voltage to word lines immediately adjacent to the selected word line, and providing the first pass voltage to word lines not immediately adjacent to the selected word line;

performing a first verify operation based on the first condition, including generating a first verify voltage by the voltage generator and providing the first verify voltage to the selected word line;
performing a second program operatio

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Junyong
• Kim Hyunggon
• Kim Byungsoo
• Joe Sungmin

Classifications

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title