Semiconductor circuit and semiconductor circuit system

Patent metadata

Field	Value
Publication number	US-11900993-B2
Application number	US-202017637312-A
Country	US
Kind code	B2
Filing date	Aug 13, 2020
Priority date	Sep 3, 2019
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A semiconductor circuit according to the present disclosure includes: a first circuit configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit configured to apply an inverted voltage of a voltage at a second node to the first node; a first storage element including first, second, and third terminals; a first transistor including a drain coupled to the first node and a source coupled to the first terminal of the first storage element; a second transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element; and a third transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element. The first storage element is configured to set a resistance state between the first terminal and the second and third terminals in accordance with a direction of a current flowing between the second and third terminals.

First claim

The invention claimed is:

1. A semiconductor circuit comprising:
a first circuit configured to generate an inverted voltage of a voltage at a first node, the first circuit being configured to apply the inverted voltage to a second node;
a second circuit configured to generate an inverted voltage of a voltage at the second node, the second circuit being configured to apply the inverted voltage to the first node;
a first storage element including a first terminal, a second terminal, and a third terminal, the first storage element being configured to set a resistance state between the first terminal, the second terminal, and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a current flowing between the second terminal and the third terminal;
a first transistor including a drain coupled to the first node, a source coupled to the first terminal of the first storage element, and a gate, the first transistor being configured to couple the first node to the first terminal of the first storage element by being turned on;
a second transistor including a gate coupled to the first node or the second node, a drain coupled to the second terminal of the first storage element, and a source, the second transistor being configured to apply a first voltage to the second terminal of the first storage element by being turned on; and
a third transistor including a gate coupled to the first node or the second node, a drain coupled to the second terminal of the first storage element, and a source, the third transistor being configured to apply a second voltage to the second terminal of the first storage element by being turned on, the second voltage being different from the first voltage.

2. The semiconductor circuit according to claim 1 , further comprising:
a second storage element including a fourth terminal, a fifth terminal, and a sixth terminal, the second storage element being configured to set a resistance state between the fourth terminal, the fifth terminal, and the sixth terminal to the first resistance state or the second resistance state in accordance with a direction of a current flowing between the fifth terminal and the sixth terminal;
a fourth transistor including a drain coupled to the second node, a source coupled to the fourth terminal of the second storage element, and a gate, the fourth transistor being configured to couple the second node to the fourth terminal of the second storage element by being turned on;
a fifth transistor including a gate coupled to a node of the first node and the second node that is different from the node to which the gate of the second transistor is coupled, a drain coupled to the fifth terminal of the second storage element, and a source, the fifth transistor being configured to apply the first voltage to the fifth terminal of the second storage element by being turned on; and
a sixth transistor including a gate coupled to a node of the first node and the second node that is different from the node to which the gate of the third transistor is coupled, a drain coupled to the fifth terminal of the second storage element, and a source, the sixth transistor being configured to apply the second voltage to the fifth terminal of the second storage element by being turned on.

3. The semiconductor circuit according to claim 2 , further comprising:
a first voltage supply section configured to supply the source of the second transistor and the source of the fifth transistor with the first voltage and configured to supply the source of the third transistor and the source of the sixth transistor with the second voltage;
a second voltage supply section configured to supply the third terminal of the first storage element and the sixth terminal of the second storage element with a control voltage; and
a control section configured to control operations of the first transistor, the fourth transistor, the first voltage supply section, and the second voltage supply section.

4. The semiconductor circuit according to claim 3 , wherein
the gate of the second transistor and the gate of the third transistor are coupled to the second node,
the gate of the fifth transistor and the gate of the sixth transistor are coupled to the first node, and
the control section is configured to
perform, in a first sub-period of a first period, a first operation of turning off the first transistor and the fourth transistor, performing control to cause the first voltage supply section to supply the source of the second transistor and the source of the fifth transistor with the first voltage, and performing control to cause the second voltage supply section to set the control voltage to a third voltage different from the first voltage, and
perform, in a second sub-period of the first period, a second operation of turning off the first transistor and the fourth transistor, performing control to cause the first voltage supply section to supply the source of the third transistor and the source of the sixth transistor with the second voltage, and performing control to cause the second voltage supply section to set the control voltage to a fourth voltage different from the second voltage.

5. The semiconductor circuit according to claim 4 , wherein the control section is configured to set the voltage at the first node to a voltage corresponding to the resistance state of the first storage element and configured to set the voltage at the second node to a voltage corresponding to the resistance state of the second storage element by turning on the first transistor and the fourth transistor in a second period after the first period.

6. The semiconductor circuit according to claim 5 , further comprising a power supply control section configured to control power supply to the first circuit and the second circuit, wherein
the power supply control section
supplies the first circuit and the second circuit with power in the first period and the second period, and
stops supplying the first circuit and the second circuit with power in a third period between the first period and the second period.

7. The semiconductor circuit according to claim 3 , wherein
the gate of the second transistor and the gate of the sixth transistor are coupled to the second node,
the gate of the third transistor and the gate of the fifth transistor are coupled to the first node, and
the control section is configured to
perform, in a first period, a third operation of turning off the first transistor and the fourth transistor, performing control to cause the first voltage supply section to supply the source of the second transistor and the source of the fifth transistor with the first voltage, and performing control to cause the second voltage supply section to set the control voltage to a third voltage different from the first voltage.

8. The semiconductor circuit according to claim 7 , wherein the control section is configured to set the voltage at the first node to a voltage corresponding to the resistance state of the first storage element and configured to set the voltage at the second node to a voltage corresponding to the resistance state of the second storage element by turning on the first transistor and the fourth transistor in a second period after the first period.

9. The semiconductor circuit according to claim 8 , further comprising a power supply control section configured to control power supply to the first circuit and the second circuit, wherein
the power supply control section
supplies the first circuit and the second circuit with power in the first period and the second period, and
stops supplying the first circuit and the second circuit with power in a third period between the first pe

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• SHUTO Yusuke

Classifications

• H10D48/40

  Devices controlled by magnetic fields · CPC title

• G11C14/00 Primary

  Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/1697

  Power supply circuits · CPC title