Semiconductor circuit and electronic device for storing information

Patent metadata

Field	Value
Publication number	US-11450369-B2
Application number	US-201917250649-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Aug 27, 2018
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A semiconductor circuit according to the present disclosure includes a first circuit that generates an inverted voltage of a voltage at a first node, and applies the inverted voltage to a second nodes, a second circuit that generates an inverted voltage of a voltage at the second node, and applies the inverted voltage to the first node, a first memory element that has a first terminal, a second terminal, and a third terminal, and stores information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state in accordance with a direction of a first current flowing between the first terminal and the second terminal, a first transistor that couples the first node to the third terminal of the first memory element and a second transistor that is coupled to a first coupling node.

First claim

The invention claimed is:

1. A semiconductor circuit, comprising:
a first circuit configured to:
generate a first inverted voltage of a voltage at a first node, and
apply the first inverted voltage to a second node;

a second circuit configured to:
generate a second inverted voltage of a voltage at the second node, and
apply the second inverted voltage to the first node;

a first memory element including a first terminal, a second terminal, and a third terminal, wherein the first memory element is configured to store information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state based on a direction of a first current flowing between the first terminal and the second terminal;
a first transistor configured to couple, by being turned on, the first node to the third terminal of the first memory element;
a second transistor coupled to a first coupling node, wherein
the second transistor is configured to control flow of the first current to the second terminal of the first memory element based on a voltage at the first coupling node,
the first coupling node is one of the first node or the second node;

a third transistor configured to supply, by being turned on, the first terminal of the first memory element with a first voltage, wherein
the second transistor has a first drain, a first gate, and a first source,
the first gate is coupled to the first coupling node, and
the first source is coupled to the first terminal of the first memory element;

a fourth transistor configured to supply, by being turned on, the first drain of the second transistor with a second voltage different from the first voltage; and
a controller configured to control operations of the first transistor, the third transistor, and the fourth transistor.

2. The semiconductor circuit according to claim 1 , wherein the controller is further configured to turn on the fourth transistor and turn off the first transistor and the third transistor in a first period, thereby setting a resistance state of the first memory element to a resistance state corresponding to a voltage at the first coupling node.

3. The semiconductor circuit according to claim 2 , wherein the controller is further configured to turn on the first transistor and turn off the third transistor and the fourth transistor in a second period after the first period, thereby setting the voltage at the first node to a voltage corresponding to the resistance state of the first memory element.

4. The semiconductor circuit according to claim 3 , further comprising a power supply transistor configured to execute, by being turned on, power supply to the first circuit and the second circuit, wherein the controller is further configured to turn off the power supply transistor in a third period between the first period and the second period.

5. The semiconductor circuit according to claim 2 , wherein the controller is further configured to turn on the third transistor and turn off the first transistor and the fourth transistor in a fourth period before the first period, thereby setting the resistance state of the first memory element to the first resistance state.

6. The semiconductor circuit according to claim 1 , wherein the first circuit and the second circuit are configured to facilitate the voltage at the first node to be set to a specific initial voltage after power is turned on.

7. The semiconductor circuit according to claim 6 , wherein
the first circuit includes a fifth transistor configured to couple, by being turned on, a first power supply to the second node, the first power supply corresponding to the specific initial voltage, and
the second circuit includes a sixth transistor configured to couple, by being turned on, the first power supply to the first node, the sixth transistor having a gate width greater than a gate width of the fifth transistor.

8. The semiconductor circuit according to claim 6 , wherein
the second circuit includes a seventh transistor configured to couple, by being turned on, a second power supply to the first node, the second power supply corresponding to a voltage different from the specific initial voltage, and
the first circuit includes an eighth transistor configured to couple, by being turned on, the second power supply to the second node, the eighth transistor having a gate width greater than a gate width of the seventh transistor.

9. The semiconductor circuit according to claim 6 , wherein
the first circuit includes a fifth transistor configured to couple, by being turned on, a first power supply to the second node, the first power supply corresponding to the specific initial voltage, and
the second circuit includes a sixth transistor configured to couple, by being turned on, the first power supply to the first node, the sixth transistor having a gate length less than a gate length of the fifth transistor.

10. The semiconductor circuit according to claim 6 , wherein
the second circuit includes a seventh transistor configured to couple, by being turned on, a second power supply to the first node, the second power supply corresponding to a voltage different from the specific initial voltage, and
the first circuit includes an eighth transistor configured to couple, by being turned on, the second power supply to the second node, the eighth transistor having a gate length less than a gate length of the seventh transistor.

11. The semiconductor circuit according to claim 6 , wherein
the second circuit includes a sixth transistor configured to couple, by being turned on, a first power supply to the first node, the first power supply corresponding to the specific initial voltage, and
a current value of a current flowing from the first power supply to the first node, when the sixth transistor is turned on, is a current value between a first current value and a second current value, wherein
the first current value is for a current flowing from the first node to the first memory element via the first transistor when the first transistor is turned on and the resistance state of the first memory element is the first resistance state, and
the second current value is for a current flowing from the first node to the first memory element via the first transistor when the first transistor is turned on and the resistance state of the first memory element is the second resistance state.

12. The semiconductor circuit according to claim 1 , further comprising:
a second memory element that has a first terminal, a second terminal, and a third terminal, wherein the second memory element is configured to store information by setting a resistance state between the second terminal of the second memory element and the third terminal of the second memory element to the first resistance state or the second resistance state based on a direction of a second current flowing between the first terminal of the second memory element and the second terminal of the second memory element;
a ninth transistor configured to couple, by being turned on, the second node to the third terminal of the second memory element;
a tenth transistor coupled to a second coupling node, wherein the tenth transistor is configured to cause the second current to flow to the second terminal of the second memory element based on a voltage at the second coupling node, the second coupling node being one of the first node or the second node and different from the first coupling node; and
an eleventh transistor configured to supply, by being turned on, the first terminal of the second memory element with the first voltage, wherein
the tenth transistor has a second

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Kanda Yasuo

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/1697 Primary

  Power supply circuits · CPC title

• G11C14/00

  Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down · CPC title