Apparatus and method to identify the source of an interrupt

Patent metadata

Field	Value
Publication number	US-11900115-B2
Application number	US-202318126920-A
Country	US
Kind code	B2
Filing date	Mar 27, 2023
Priority date	Mar 28, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores, each core of the plurality of cores comprising decode circuitry to decode instructions and execution circuitry to execute the instructions and process data;
a plurality of programmable interrupt controllers, each programmable interrupt controller associated with one or more cores of plurality of cores and to manage interrupt information for processing interrupts, including non-markable interrupts (NMIs), at least one of the programmable interrupt controllers comprising:
local interrupt processing circuitry including a plurality of registers to store entries of a local vector table (LVT), each entry of the LVT comprising a first plurality of fields to store information associated with a corresponding interrupt, the first plurality of fields including a first delivery mode field and a first vector field, wherein responsive to an NMI from a local NMI source, the first delivery mode field in a corresponding entry to store an indication of an NMI delivery mode, and the first vector field in the corresponding entry to store an indication of the local NMI source; and
inter-processor interrupt (IPI) processing circuitry comprising an interrupt command register (ICR) to store a second plurality of fields associated with an IPI, the second plurality of fields including a second delivery mode field and a second vector field, wherein based on an inter-processor NMI, the second delivery mode field in the ICR to store an indication of an NMI delivery mode and the second vector field to store an indication of a source of the inter-processor NMI.

2. The processor of claim 1 wherein the first vector field is to be written with a first source value based on the local NMI source, wherein the first source value is to be read and translated into a first bitmask in which at least one bit is set to identify the local NMI source.

3. The processor of claim 2 wherein the first source value comprises an 8-bit value and the first bitmask comprises a 16-bit bitmask.

4. The processor of claim 1 wherein the second vector field is to be written with a second source value based on the source of the inter-processor NMI, wherein the second source value is to be read and translated into a second bitmask in which at least one bit is set to identify the source of the inter-processor NMI.

5. The processor of claim 4 wherein the second source value comprises an 8-bit value and the second bitmask comprises a 16-bit bitmask.

6. The processor of claim 1 further comprising:
an input/output memory management unit (IOMMU) to map regions of system memory to system devices, including input/output (IO) devices, the IOMMU comprising circuitry to process interrupts associated with system devices.

7. The processor of claim 6 wherein the IOMMU is to process the interrupts with an interrupt remapping table comprising a plurality of entries, each entry corresponding to an interrupt associated with a system device, wherein each entry comprises a third delivery mode field and a third vector field, wherein responsive to an NMI associated with a system device, the IOMMU circuitry is to update the third delivery mode field to indicate an NMI delivery mode and is to update the third vector field to indicate a source of the NMI associated with the system device.

Assignees

• Intel Corp

Inventors

• Raj Ashok
• Kleen Andreas
• Neiger Gilbert
• Strong Beeman
• Brandt Jason
• Vakharwala Rupin
• Huxel Jeff
• Novakovsky Larisa
• Ouziel Ido
• Jayakumar Sarathy

Classifications

• G06F9/30098 Primary

  Register arrangements · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/5005

  to service a request · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F2209/481

  Exception handling · CPC title