Printed circuit board

Patent metadata

Field	Value
Publication number	US-11895771-B2
Application number	US-202117189756-A
Country	US
Kind code	B2
Filing date	Mar 2, 2021
Priority date	Nov 23, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A printed circuit board includes: a first insulating layer; a via pad including a first layer embedded in the first insulating layer and a second layer disposed on the first layer; and a first via layer disposed on the via pad, wherein the second layer has a width decreasing in a direction away from the first layer in a stacking direction of the first and second layers.

First claim

What is claimed is:

1. A printed circuit board comprising:
a first insulating layer;
a second insulating layer disposed on the first insulating layer;
a via pad including a first layer embedded in the first insulating layer and a second layer disposed on the first layer and embedded in the second insulating layer, the second layer directly contacting the first layer; and
a first via layer disposed on one side of the via pad, connected to the first layer and penetrating through at least a portion of the first insulating layer, and a second via layer disposed on an opposing side of the via pad, connected to the second layer and penetrating through at least a portion of the second insulating layer,
wherein the second layer has a width decreasing in a direction away from the first layer in a stacking direction of the first and second layers,
each of the first and second layers of the via pad includes a metal material,
the second via layer is in contact with the second layer and has a tapered side surface, and
each of the first and second insulating layers is a single layer.

2. The printed circuit board of claim 1 , wherein a width of the first layer is greater than a width of the second layer.

3. The printed circuit board of claim 2 , wherein the second layer protrudes from a first surface of the first insulating layer.

4. The printed circuit board of claim 3 , wherein an interface is formed between the first layer and the second layer.

5. The printed circuit board of claim 4 , wherein a heterogeneous metal layer is formed on the interface, and
the first via layer has a width increasing in a direction away from the via pad in the stacking direction.

6. The printed circuit board of claim 5 , further comprising a fine circuit unit embedded in the first insulating layer,
wherein the fine circuit unit is disposed on the same level as the first layer of the via pad, the fine circuit unit overlapping the first layer in a width direction perpendicular to the stacking direction.

7. The printed circuit board of claim 6 , further comprising build-up structures disposed on the first surface and a second surface of the first insulating layer, and including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers,
wherein the build-up structure disposed on the first surface of the first insulating layer includes the second insulating layer and the second via layer.

8. The printed circuit board of claim 7 , wherein when an average pitch of the fine circuit unit is defined as a first pitch and an average pitch of at least one of the plurality of wiring layers is defined as a second pitch, the first pitch is narrower than the second pitch.

9. A printed circuit board comprising:
a first insulating layer;
a second insulating layer disposed on the first insulating layer;
a via pad and a fine circuit unit at least partially embedded in the first insulating layer;
a first via layer penetrating through at least a portion of the first insulating layer and disposed on one side of the via pad in a stacking direction; and
a second via layer penetrating through at least a portion of the second insulating layer and disposed on an opposing side of the via pad in a stacking direction,
wherein the via pad has a step portion,
the via pad includes a first layer and a second layer, the second layer being disposed on and directly contacting a first surface of the first layer,
each of the first and second layers of the via pad includes a metal material, the first and second layers of the via pad are distinct layers having a physical interface therebetween, and
each of the first and second insulating layers is a single layer.

10. The printed circuit board of claim 9 , wherein the via pad and the fine circuit unit are disposed on the same level and overlap each other in a width direction perpendicular to the stacking direction.

11. The printed circuit board of claim 9 , wherein the via pad has a greater thickness than the fine circuit unit.

12. The printed circuit board of claim 9 , wherein the first layer has a greater width than the second layer.

13. The printed circuit board of claim 12 , wherein the first via layer is in contact with the second layer to be electrically connected thereto.

14. The printed circuit board of claim 13 , wherein the via pad further includes a third layer disposed on a second surface of the first layer opposite to the first surface of the first layer,
the first and second layers are embedded in the first insulating layer, and
the third layer protrudes from a first surface of the first insulating layer and is embedded in the second insulating layer.

15. The printed circuit board of claim 14 , wherein the third layer has a width decreasing in a direction away from the first layer in a stacking direction of the first and second layers.

16. The printed circuit board of claim 15 , further comprising build-up structures disposed on the first surface and a second surface of the first insulating layer, and including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers,
wherein the build-up structure disposed on the second surface of the first insulating layer includes the second insulating layer and the second via layer.

17. A printed circuit board comprising:
a first insulating layer having a first surface and a second surface opposing each other in a stacking direction;
a second insulating layer disposed on the first surface of the first insulating layer;
a via pad at least partially embedded in the first insulating layer;
a fine circuit unit embedded in the first insulating layer, exposed to the first surface of the first insulating layer, and disposed adjacent to a side of the via pad in a width direction perpendicular to the stacking direction;
a first via layer embedded in the first insulating layer, exposed to the second surface of the first insulating layer, and connected to one side of the via pad; and
a second via layer embedded in the second insulating layer and connected to an opposing side of the via pad,
wherein the fine circuit unit is not in direct contact with any conductive element, and each of the first and second insulating layers is a single layer.

18. The printed circuit board of claim 17 , wherein the via pad includes a first layer embedded in the first insulating layer and a second layer disposed on the first layer and embedded in the second insulating layer, and the second layer protruding from the first surface of the first insulating layer.

19. The printed circuit board of claim 18 , wherein the first layer of the via pad has a reduced-width portion that is connected to the first via layer, and
a thickness of the via pad is greater than a thickness of the fine circuit unit.

20. The printed circuit board of claim 17 , further comprising build-up structures disposed on the first surface and the second surface of the first insulating layer, and including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers,
wherein the build-up structure disposed on the first surface of the first insulating layer includes the second insulating layer and the second via layer.

Assignees

• Samsung Electro Mech

Inventors

• Lee Jin Uk
• Cho Young Ook
• Kim Eun Sun
• You Young Hun

Classifications

• H05K1/113 Primary

  Via provided in pad; Pad over filled via · CPC title

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title

• H05K1/02 Primary

  Details · CPC title

• H05K1/111 Primary

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K1/182

  associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] · CPC title