Substrate integrated waveguide transition including an impedance transformer having an open portion with long sides thereof parallel to a centerline

US11894595B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11894595-B2
Application numberUS-202218059655-A
CountryUS
Kind codeB2
Filing dateNov 29, 2022
Priority dateDec 28, 2020
Publication dateFeb 6, 2024
Grant dateFeb 6, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Example embodiments relate to substrate integrated waveguide (SIW) transitions. An example SIW may include a dielectric substrate having a top surface and a bottom surface and a first metallic layer portion coupled to the top surface of the dielectric substrate that includes a single-ended termination, an impedance transformer, and a metallic rectangular patch located within an open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch. The SIW also includes a second metallic layer portion coupled to the bottom surface of the dielectric substrate and metallic via-holes electrically coupling the first metallic layer to the second metallic layer. The SIW may be implemented in a radar unit to couple antennas to a printed circuit board (PCB). In some examples, the SIW may be implemented with only a non-conductive opening that lacks the metallic rectangular patch.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a dielectric substrate having a top surface and a bottom surface; a first metallic layer portion coupled to the top surface of the dielectric substrate, wherein the first metallic layer portion comprises: a single-ended termination, and an impedance transformer positioned between the single-ended termination and an open portion in the first metallic layer portion, wherein the impedance transformer tapers from a first end positioned proximate the single-ended termination to a second end positioned proximate the open portion, and wherein the open portion has a rectangular configuration with long sides thereof aligned in parallel to a centerline that extends between the single-ended termination and the impedance transformer; a second metallic layer portion coupled to the bottom surface of the dielectric substrate; and a set of metallic via-holes electrically coupling the first metallic layer portion to the second metallic layer portion. 2. The apparatus of claim 1 , wherein the top surface and the bottom surface of the dielectric substrate are printed circuit board (PCB) laminate, and wherein the first metallic layer portion is coupled to the PCB laminate. 3. The apparatus of claim 1 , wherein the first metallic layer portion is coupled to a first half of the top surface of the dielectric substrate with only the impedance transformer and the single-ended termination coupled to a second half of the top surface of the dielectric substrate. 4. The apparatus of claim 1 , wherein the single-ended termination is configured to couple to a transmission line on a PCB. 5. The apparatus of claim 4 , wherein the single-ended termination is configured to couple a first signal from the transmission lines on the PCB into a waveguide via the open portion, wherein the waveguide is positioned proximate the open portion, and wherein the single-ended termination is configured to couple a second signal from the waveguide to the transmission lines on the PCB via the open portion. 6. The apparatus of claim 1 , wherein the set of metallic via-holes comprises: a pair of parallel lines of metallic via-holes extending in parallel relative to the long sides of the open portion such that the open portion is located between the pair of parallel lines of metallic via-holes; and a baseline of metallic via-holes extending between ends of the pair of parallel lines of metallic via-holes and in parallel relative to short sides of the open portion. 7. The apparatus of claim 6 , wherein the pair of parallel lines of metallic via-holes are equal in length, and wherein a length of each parallel line of metallic via-holes is greater than a given length of the baseline of metallic via-holes. 8. The apparatus of claim 1 , wherein the first metallic layer portion is configured to couple to a waveguide such that electromagnetic energy is able to propagate through the open portion and into the waveguide. 9. The apparatus of claim 1 , wherein the first metallic layer portion includes a metallic rectangular patch positioned located within the open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch. 10. A system comprising: a waveguide; a substrate integrated waveguide (SIW) transition coupled to the waveguide, wherein the SIW transition comprises: a dielectric substrate having a top surface and a bottom surface; a first metallic layer portion coupled to the top surface of the dielectric substrate, wherein the first metallic layer portion comprises: a single-ended termination, and an impedance transformer positioned between the single-ended termination and an open portion in the first metallic layer portion, wherein the impedance transformer tapers from a first end positioned proximate the single-ended termination to a second end positioned proximate the open portion, and wherein the open portion has a rectangular configuration with long sides thereof aligned in parallel to a centerline that extends between the single-ended termination and the impedance transformer; a second metallic layer portion coupled to the bottom surface of the dielectric substrate; and a set of metallic via-holes electrically coupling the first metallic layer portion to the second metallic layer portion. 11. The system of claim 10 , wherein the first metallic layer portion includes a metallic rectangular patch positioned located within the open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch. 12. The system of claim 10 , wherein the top surface and the bottom surface of the dielectric substrate are printed circuit board (PCB) laminate, and wherein the first metallic layer portion is coupled to the PCB laminate. 13. The system of claim 10 , wherein the first metallic layer portion is coupled to a first half of the top surface of the dielectric substrate with only the impedance transformer and the single-ended termination coupled to a second half of the top surface of the dielectric substrate. 14. The system of claim 10 , further comprising: a printed circuit board (PCB) having a transmission line; and wherein the single-ended termination is configured to couple to the transmission line on the PCB. 15. The system of claim 14 , wherein the single-ended termination is configured to couple a first signal from the transmission lines on the PCB into the waveguide via the SIW transition, and wherein the single-ended termination is configured to couple a second signal from the waveguide to the transmission lines on the PCB via the SIW transition. 16. The system of claim 14 , wherein the pair of parallel lines of metallic via-holes are equal in length, and wherein the length of the parallel lines of metallic via-holes is greater than a given length of the baseline of metallic via-holes. 17. The system of claim 10 , wherein the set of metallic via-holes comprises: a pair of parallel lines of metallic via-holes extending in parallel relative to the long sides of the open portion such that the open portion is located between the pair of parallel lines of metallic via-holes; and a baseline of metallic via-holes extending between ends of the pair of parallel lines of metallic via-holes and in parallel relative to short sides of the open portion. 18. A method comprising: conducting electromagnetic energy via a transmission line on a printed circuit board (PCB); coupling the electromagnetic energy into a waveguide via an SIW transition, wherein the SIW transition comprises: a dielectric substrate having a top surface and a bottom surface; a first metallic layer portion coupled to the top surface of the dielectric substrate, wherein the first metallic layer portion comprises: a single-ended termination, and an impedance transformer positioned between the single-ended termination and an open portion in the first metallic layer portion, wherein the impedance transformer tapers from a first end positioned proximate the single-ended termination to a second end positioned proximate the open portion, and wherein the open portion has a rectangular configuration with long sides thereof aligned in parallel to a centerline that extends between the single-ended termination and the impedance transformer; a second metallic layer portion coupled to the bottom surface of the dielectric substrate; and a set of metallic via-holes electrically coupling the first metallic layer portion to the second metallic layer p

Assignees

Inventors

Classifications

  • H01P5/107Primary

    Hollow-waveguide/strip-line transitions · CPC title

  • Multilayer dielectric · CPC title

  • integrated in a substrate · CPC title

  • Dielectric details, e.g. changing the dielectric material around a transmission line · CPC title

  • Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure · CPC title

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Frequently asked questions

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What does patent US11894595B2 cover?
Example embodiments relate to substrate integrated waveguide (SIW) transitions. An example SIW may include a dielectric substrate having a top surface and a bottom surface and a first metallic layer portion coupled to the top surface of the dielectric substrate that includes a single-ended termination, an impedance transformer, and a metallic rectangular patch located within an open portion in …
Who is the assignee on this patent?
Waymo Llc
What technology area does this patent fall under?
Primary CPC classification H01P5/107. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 06 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).