Substrate integrated waveguide transition including a metallic layer portion having an open portion that is aligned offset from a centerline

Patent metadata

Field	Value
Publication number	US-11539107-B2
Application number	US-202017135268-A
Country	US
Kind code	B2
Filing date	Dec 28, 2020
Priority date	Dec 28, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Example embodiments relate to substrate integrated waveguide (SIW) transitions. An example SIW may include a dielectric substrate having a top surface and a bottom surface and a first metallic layer portion coupled to the top surface of the dielectric substrate that includes a single-ended termination, an impedance transformer, and a metallic rectangular patch located within an open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch. The SIW also includes a second metallic layer portion coupled to the bottom surface of the dielectric substrate and metallic via-holes electrically coupling the first metallic layer to the second metallic layer. The SIW may be implemented in a radar unit to couple antennas to a printed circuit board (PCB). In some examples, the SIW may be implemented with only a non-conductive opening that lacks the metallic rectangular patch.

First claim

What is claimed is:

1. An apparatus comprising:
a dielectric substrate having a top surface and a bottom surface;
a first metallic layer portion coupled to the top surface of the dielectric substrate, wherein the first metallic layer portion comprises:
a single-ended termination,
an impedance transformer, and
a metallic rectangular patch located within an open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch, wherein a centerline extends through a center of the single-ended termination and a center of the impedance transformer, and wherein the open portion is aligned offset relative to the centerline;

a second metallic layer portion coupled to the bottom surface of the dielectric substrate; and
a set of metallic via-holes electrically coupling the first metallic layer portion to the second metallic layer portion.

2. The apparatus of claim 1 , wherein the top surface and the bottom surface of the dielectric substrate include a printed circuit board (PCB) laminate, and wherein the first metallic layer portion is coupled to the PCB laminate.

3. The apparatus of claim 1 , wherein the first metallic layer portion is coupled to a first half of the top surface of the dielectric substrate with only the impedance transformer and the single-ended termination coupled to a second half of the top surface of the dielectric substrate.

4. The apparatus of claim 1 , wherein the single-ended termination is configured to couple to a transmission line on a PCB.

5. The apparatus of claim 4 , wherein the single-ended termination is configured to couple a first signal from the PCB into a waveguide via a combination of the metallic rectangular patch and the non-conductive loop, and wherein the single-ended termination is configured to couple a second signal from the waveguide to the PCB via the combination of the metallic rectangular patch and the non-conductive loop.

6. The apparatus of claim 1 , wherein the impedance transformer includes a tapered transition configuration.

7. The apparatus of claim 1 , wherein the first metallic layer portion is configured to couple to a waveguide such that electromagnetic energy is able to propagate between the metallic rectangular patch and the waveguide.

8. The apparatus of claim 1 , wherein the set of metallic via-holes comprises:
a pair of parallel lines of metallic via-holes extending in parallel relative to a length of the metallic rectangular patch such that the metallic rectangular patch is located between the pair of parallel lines of metallic via-holes; and
a baseline of metallic via-holes extending between ends of the pair of parallel lines of metallic via-holes and in parallel relative to a width of the metallic rectangular patch.

9. The apparatus of claim 8 , wherein the pair of parallel lines of metallic via-holes are equal in length, and wherein a length of each parallel line of metallic via-holes is greater than a given length of the baseline of metallic via-holes.

10. A method comprising:
conducting electromagnetic energy via a transmission line on a printed circuit board (PCB);
coupling the electromagnetic energy into a waveguide via an SIW transition, wherein the SIW transition comprises:
a dielectric substrate having a top surface and a bottom surface;
a first metallic layer portion coupled to the top surface of the dielectric substrate, wherein the first metallic layer portion comprises: (i) a single-ended termination, (ii) an impedance transformer, and (iii) a metallic rectangular patch located within an open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch, wherein a centerline extends through a center of the single-ended termination and a center of the impedance transformer, and wherein the open portion is aligned offset relative to the centerline;
a second metallic layer portion coupled to the bottom surface of the dielectric substrate; and
a set of metallic via-holes electrically coupling the first metallic layer portion to the second metallic layer portion; and
transmitting the electromagnetic energy as signals via one or more antennas coupled to the waveguide.

11. The method of claim 10 , further comprising:
receiving one or more signals from the one or more antennas coupled to the waveguide; and
coupling electromagnetic energy corresponding to the one or more signals from the waveguide and to the PCB via the SIW transition.

12. A system comprising:
a waveguide;
a substrate integrated waveguide (SIW) transition coupled to the waveguide, wherein the SIW transition comprises:
a dielectric substrate having a top surface and a bottom surface;
a first metallic layer portion coupled to the top surface of the dielectric substrate, wherein the first metallic layer portion comprises:
a single-ended termination,
an impedance transformer, and
a metallic rectangular patch located within an open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch, wherein a centerline extends through a center of the single-ended termination and a center of the impedance transformer, and

wherein the open portion is aligned offset relative to the centerline;

a second metallic layer portion coupled to the bottom surface of the dielectric substrate; and
a set of metallic via-holes electrically coupling the first metallic layer portion to the second metallic layer portion.

13. The system of claim 12 , wherein the first metallic layer portion is coupled to a first half of the top surface of the dielectric substrate with only the impedance transformer and the single-ended termination coupled to a second half of the top surface of the dielectric substrate.

14. The system of claim 12 , further comprising:
a printed circuit board (PCB) having a transmission line; and
wherein the single-ended termination is configured to couple to the transmission line on the PCB.

15. The system of claim 14 , wherein the single-ended termination is configured to couple a first signal from the PCB into the waveguide via the SIW transition, and
wherein the single-ended termination is configured to couple a second signal from the waveguide to the PCB via the SIW transition.

16. The system of claim 12 , wherein the top surface and the bottom surface of the dielectric substrate include a printed circuit board (PCB) laminate, and wherein the first metallic layer portion is coupled to the PCB laminate.

17. The system of claim 12 , wherein the set of metallic via-holes comprises:
a pair of parallel lines of metallic via-holes extending in parallel relative to a length of the metallic rectangular patch such that the metallic rectangular patch is located between the pair of parallel lines of metallic via-holes; and
a baseline of metallic via-holes extending between ends of the pair of parallel lines of metallic via-holes and in parallel relative to a width of the metallic rectangular patch.

18. The system of claim 17 , wherein the pair of parallel lines of metallic via-holes are equal in length, and wherein the length of the parallel lines of metallic via-holes is greater than a given length of the baseline of metallic via-holes.

Assignees

• Waymo Llc

Inventors

• Lim Edwin
• Argo Tegan
• Weinstein Marvin

Classifications

• H01P5/107 Primary

  Hollow-waveguide/strip-line transitions · CPC title

• H05K1/0219

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H05K1/024

  Dielectric details, e.g. changing the dielectric material around a transmission line · CPC title

• H01P3/082

  Multilayer dielectric · CPC title

• H05K2201/0195

  Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure · CPC title