Silicon photonic integrated lens compatible with wafer processing

Patent metadata

Field	Value
Publication number	US-11894474-B2
Application number	US-201916562889-A
Country	US
Kind code	B2
Filing date	Sep 6, 2019
Priority date	Sep 6, 2019
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.

First claim

What is claimed is:

1. A semiconductor die, comprising:
a semiconductor substrate having a first surface and a second surface;
a first lens and a second lens over the first surface, the second lens laterally spaced apart from the first lens; and
an optically transparent layer over the first lens and the second lens, wherein a first surface of the optically transparent layer is conformal to a surface of the first lens and the second lens and to the first surface of the semiconductor substrate, and wherein a second surface of the optically transparent layer is substantially flat over the first lens and the second lens and between the first lens and the second lens, the second surface opposite the first surface.

2. The semiconductor die of claim 1 , wherein the optically transparent layer is over the entire first surface.

3. The semiconductor die of claim 1 , wherein a maximum thickness of the optically transparent layer is approximately 100 μm or less.

4. The semiconductor die of claim 3 , wherein the maximum thickness of the optically transparent layer is approximately 20 μm or less.

5. The semiconductor die of claim 1 , wherein the optically transparent layer comprises a polymer.

6. The semiconductor die of claim 5 , wherein the optically transparent layer comprises poly (para-xylylene) or structural analogs thereof.

7. The semiconductor die of claim 1 , further comprising:
an antireflective coating over the optically transparent layer.

8. The semiconductor die of claim 1 , wherein the first lens and the second lens are part of the semiconductor substrate.

9. The semiconductor die of claim 1 , wherein the semiconductor substrate is a silicon substrate.

10. The semiconductor die of claim 1 , wherein the semiconductor die is a photonics die.

11. A semiconductor die, comprising:
a semiconductor substrate having a first surface and a second surface;
a lens over the first surface; and
an optically transparent layer over the lens, wherein the optically transparent layer comprises a polymer comprising poly (para-xylylene) or structural analogs thereof.

Assignees

• Intel Corp

Inventors

• Dobriyal Priyanka
• Agrawal Ankur
• Jadhav Susheel
• Tran Quan
• Narayan Raghuram
• Aspandiar Raiyomand
• Brown Kenneth
• Heck John

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10F77/953

  for devices having potential barriers · CPC title

• H10F77/933

  for devices having potential barriers · CPC title