Memory device with fixed negative charge plug

Patent metadata

Field	Value
Publication number	US-11894431-B2
Application number	US-202117231515-A
Country	US
Kind code	B2
Filing date	Apr 15, 2021
Priority date	Oct 16, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.

First claim

What is claimed is:

1. A memory device comprising:
a stack structure including word lines and a select line;
a vertical hole vertically penetrating the stack structure; and
a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole,
wherein the plug includes a material layer having a fixed negative charge, and
wherein a bottom surface of the material layer is located between a bottom surface and a top surface of the select line.

2. The memory device of claim 1 , wherein the material layer includes an Al2O3 layer.

3. The memory device of claim 1 , wherein the plug includes:
a first insulating layer;
the material layer formed on the first insulating layer; and
a capping pattern formed on the material layer.

4. The memory device of claim 3 , wherein the first insulating layer includes an oxide layer, and
the capping pattern includes doped silicon.

5. The memory device of claim 3 , wherein the material layer is formed at a position adjacent to the select line in the plug.

6. The memory device of claim 5 , wherein a top surface of the material layer is located in a region higher than the top surface of the select line.

7. The memory device of claim 1 , wherein the plug includes a first insulating layer, the material layer, and a second insulating layer, and
wherein the material layer is disposed between the first and second insulating layers.

8. The memory device of claim 7 , wherein a top surface of the material layer is located at a height greater than a height at which the top surface of the select line is located.

9. The memory device of claim 1 , wherein the plug includes a first insulating layer and the material layer, and
wherein a position of a top surface of the material layer is equal to that of a top surface of the plug.

10. A memory device comprising:
a stack structure including first select lines adjacent to bit lines, second select lines adjacent to a source line, and word lines between the first and second select lines;
a vertical hole vertically penetrating the stack structure; and
a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole,
wherein the plug includes a material layer having a fixed negative charge, and
wherein a bottom surface of the material layer is located between a bottom surface of a first select line located at a lowermost end among the first select lines and a top surface of a first select line located at an uppermost end among the first select lines.

11. The memory device of claim 10 , wherein the material layer includes an Al2O3 layer.

12. The memory device of claim 10 , wherein the plug includes:
a first insulating layer;
the material layer formed on the first insulating layer; and
a capping pattern formed on the material layer.

13. The memory device of claim 12 , wherein the capping pattern includes doped silicon.

14. The memory device of claim 10 , wherein the plug includes a first insulating layer, the material layer, and a second insulating layer, and
wherein the material layer is disposed between the first and second insulating layers.

15. The memory device of claim 14 , wherein a top surface of the material layer is located on the top of the top surface of the first select line located at the uppermost end among the first select lines.

16. The memory device of claim 10 , wherein the plug includes a first insulating layer and the material layer, and
wherein a position of a top surface of the material layer is equal to that of a top surface of the plug.

Assignees

• Sk Hynix Inc

Inventors

• Yun dae hwan
• Choi Gil Bok

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D64/118 Primary

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H01L29/408 Primary

  Electricity · mapped topic