Proximity sensor

US11894339B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11894339-B2
Application numberUS-202017121198-A
CountryUS
Kind codeB2
Filing dateDec 14, 2020
Priority dateDec 14, 2020
Publication dateFeb 6, 2024
Grant dateFeb 6, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of manufacturing a sensor device includes obtaining a semiconductor die structure comprising a transmitter and a receiver. Then, a first sacrificial stud is affixed to the transmitter and a second sacrificial stud is affixed to the receiver. The semiconductor die is affixed to a lead frame, and pads on the semiconductor die structure are wirebonded to the lead frame. The lead frame, the semiconductor die structure, and the wirebonds are encapsulated in a molding compound, while the tops of the first and second sacrificial studs are left exposed. The first and second sacrificial studs prevent the molding compound from encapsulating the transmitter and the receiver, and are removed to expose the transmitter in a first cavity and the receiver in a second cavity. In some examples, the semiconductor die structure includes a first semiconductor die comprising the transmitter and a second semiconductor die comprising the receiver.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: forming a first structure on a first circuit; forming a second structure on a second circuit; encapsulating the first and second circuits and at least a part of the first and second structures with a molding compound; removing the first structure from the molding compound to form a first cavity over the first circuit; removing the second structure from the molding compound to form a second cavity over the second circuit; and forming a second material different from the molding compound in at least part of one of the first and second cavities. 2. The method of claim 1 , wherein the first circuit is on a first semiconductor die, the second circuit is on a second semiconductor die, and encapsulating the first and second circuits includes encapsulating the first and second semiconductor dies. 3. The method of claim 1 , wherein the molding compound is a first molding compound, and the second material includes a second molding compound. 4. The method of claim 1 , wherein the first circuit includes a light transmitter, the second circuit includes a light receiver, and the second material transmits light. 5. The method of claim 1 , wherein the molding compound provides a barrier between the first and second cavities. 6. The method of claim 1 , each of the first and second structures includes a respective tapered stud. 7. The method of claim 1 , wherein each of the first and second structures has a respective polygon shape or a respective circular shape. 8. The method of claim 1 , wherein each of the first and second structures includes a metal, and the first and second structures are removed with etching. 9. The method of claim 1 , wherein each of the first and second structures includes a plastic or photoresist, and the first and second structures are removed by a solvent. 10. The method of claim 1 , further comprising: affixing the first structure on the first circuit with a first adhesive; affixing the second structure on the second circuit with a second adhesive; removing the first adhesive with a first solvent; and removing the second adhesive with a second solvent. 11. The method of claim 1 , wherein the first structure covers the first circuit entirely, and the second structure covers the second circuit entirely. 12. The method of claim 1 , wherein each of the first and second structures includes a respective ring. 13. The method of claim 1 , wherein each of the first and second structures includes a respective cylindrical stud. 14. The method of claim 1 , further comprising: attaching one or more semiconductor dies including the first and second circuits on a lead frame; and forming electrical connections between the first and second circuits and the lead frame, wherein encapsulating the first and second circuits with a molding compound includes encapsulating the one or more semiconductor dies, the lead frame, and the electrical connections with the molding compound.

Assignees

Inventors

Classifications

  • characterised by their shape or disposition · CPC title

  • Die-attach connectors and bond wires · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between laterally-adjacent chips · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

Patent family

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External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11894339B2 cover?
A method of manufacturing a sensor device includes obtaining a semiconductor die structure comprising a transmitter and a receiver. Then, a first sacrificial stud is affixed to the transmitter and a second sacrificial stud is affixed to the receiver. The semiconductor die is affixed to a lead frame, and pads on the semiconductor die structure are wirebonded to the lead frame. The lead frame, th…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 06 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).