Semiconductor processing systems with in-situ electrical bias

Patent metadata

Field	Value
Publication number	US-11894240-B2
Application number	US-202117185231-A
Country	US
Kind code	B2
Filing date	Feb 25, 2021
Priority date	Apr 6, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

First claim

What is claimed is:

1. A system for processing semiconductor wafers, the system comprising:
a processing chamber;
a heat source;
a substrate holder configured to expose a semiconductor wafer to the heat source;
a first electrode configured to be detachably attached to the semiconductor wafer, a conductive outer surface of the first electrode configured to be in physical contact with a first major surface of the semiconductor wafer when the first electrode is attached detachably to the semiconductor wafer; and
a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

2. The system of claim 1 , further comprising a control system comprising a measurement probe configured to measure a current-voltage curve through a layer of the semiconductor wafer when the electric field is being applied, the control system comprising a controller to control the electric field.

3. The system of claim 1 , wherein the heat source is a hot plate positioned below a backside of the semiconductor wafer.

4. The system of claim 3 ,
wherein the hot plate comprises a substrate having an outer surface comprising an electrically insulating layer, and
wherein the electrically insulating layer is covered by an electrically conductive plate, the electrically conductive plate configured to being electrically coupled to the backside of the semiconductor wafer.

5. The system of claim 3 , wherein the hot plate is an electrically conductive material, the hot plate configured to being electrically coupled to the backside of the semiconductor wafer.

6. The system of claim 1 , wherein the heat source comprises a plurality of heat sources configured to radiatively heat the semiconductor wafer.

7. The system of claim 1 , wherein the heat source is disposed outside the processing chamber and configured to heat the semiconductor wafer by radiative heat transfer.

8. The system of claim 1 , wherein the heat source is disposed inside the processing chamber and configured to heat the semiconductor wafer by radiative heat transfer.

9. The system of claim 1 , wherein the heat source comprises a resistive heat source.

10. The system of claim 9 , wherein the heat source comprises a mineral insulated (MI) cable, a resistor coated with a ceramic, or a graphite resistor coated with a pyrolytic boron nitride (PBN).

11. The system of claim 1 , wherein the heat source comprises an infrared (IR) lamp, an ultraviolet (UV) lamp, or a flash arc lamp.

12. The system of claim 1 , wherein the electric field is configured to be applied by
maintaining a fixed voltage across the first electrode and the second electrode, or
maintaining a time-varying voltage across the first electrode and the second electrode, wherein the time-varying voltage comprises a pulsed voltage or a sinusoidal voltage.

13. The system of claim 1 , wherein the first electrode or the second electrode is coupled to a floating potential node.

14. The system of claim 1 , further comprising:
a scanner,
wherein the heat source is a source for a laser beam, the laser beam being configured to heat a portion of a major surface of the semiconductor wafer intersecting with the laser beam, and
wherein the scanner is configured to move the portion of the major surface intersecting with the laser beam to expose all of the major surface to the laser beam.

15. The system of claim 1 , further comprising:
a fluid inlet and a fluid outlet disposed in the processing chamber; and
a heater coil configured to heat a fluid flowing into the processing chamber.

16. The system of claim 1 , further comprising:
a cluster of modules comprising an equipment front end module, a wafer transfer module, and a processing module, the processing chamber being part of the processing module.

17. A system for annealing a semiconductor wafer, the system comprising:
a processing chamber;
a heat source;
a substrate holder configured to anneal the semiconductor wafer by exposing to the heat source;
a first electrode configured to be detachably attached to a first major surface of the semiconductor wafer, a conductive outer surface of the first electrode making direct electrical contact with the first major surface of the semiconductor wafer; and
a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer during the annealing.

18. The system of claim 17 , further comprising a control system comprising a measurement probe configured to measure a current-voltage curve through a layer of the semiconductor wafer when the electric field is being applied, the control system comprising a controller to control the electric field.

19. The system of claim 17 , wherein the heat source is a hot plate positioned below a backside of the semiconductor wafer.

20. A system for processing a semiconductor wafer, the system comprising:
a processing chamber;
a heat source;
a substrate holder configured to expose the semiconductor wafer to the heat source;
a first electrode configured to be detachably attached to the semiconductor wafer, an outer surface of the first electrode configured to be in physical contact with a first major surface of the semiconductor wafer when the first electrode is attached detachably to the semiconductor wafer;
a power supply coupled to the first electrode;
a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer;
a third electrode physically separate from the first electrode and configured to be detachably attached to the semiconductor wafer, an outer surface of the third electrode configured to be in physical contact with the first major surface of the semiconductor wafer when the third electrode is attached detachably to the semiconductor wafer; and
a voltmeter coupled between the third electrode and a reference potential, the voltmeter being configured to monitor an electric potential on the first major surface of the semiconductor wafer.

21. The system of claim 20 , wherein the heat source is a hot plate positioned below a backside of the semiconductor wafer.

22. The system of claim 20 , wherein the heat source comprises a resistive heat source.

23. The system of claim 1 ,
wherein the first electrode is further configured to be in physical contact with a first conductive layer at the first major surface of the semiconductor wafer, and
wherein the second electrode is physically separate from the first electrode and is configured to be detachably attached to the semiconductor wafer, a conductive surface of the second electrode configured to be in physical contact with a second conductive layer of the first major surface.

Assignees

• Tokyo Electron Ltd

Inventors

• Hurley David
• Domsa Ioan
• Colgan Ian
• Van Der Linde Gerhardus
• Hughes Patrick
• Burel Maciej
• Clarke Barry
• Popovici Mihaela Ioana
• Ragnarsson Lars-Ake
• Leusink Gerrit J
• Clark Robert
• Triyoso Dina

Classifications

• H10P34/00

  Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10D64/0114

  to diamond, semiconducting diamond-like carbon or graphene · CPC title

• H10P95/80 Primary

  Electrical treatments, e.g. for electroforming · CPC title

• H10P72/0436

  mainly by radiation · CPC title