Charge sensing device with gate voltage selected to operate around the charge neutrality point and tune the quantum capacitance

Patent metadata

Field	Value
Publication number	US-11892473-B2
Application number	US-202017427505-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Jan 31, 2019
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

The present invention relates to a system comprising an electronic apparatus which comprises: —an electronic device comprising: —a gate electrode (G, BE); —a dielectric (D) arranged over the gate electrode (G, BE); and —a charge sensing structure (CE) with a 2-dimensional charge sensing layer to provide a gate capacitance (C g ) between the charge sensing structure (CE) and the gate electrode structure (G, BE) and a quantum capacitance (C q ) resulting in a total capacitance (C tot ); —a voltage detector to detect an output voltage (V o ) stored in the total capacitance (C tot ). The system further comprises means to apply a gate voltage (V g ) to the gate electrode structure (G, BE) selected to: —make the device operate around most sensitive point of fermi level of the charge sensing structure (CE); and —tune the quantum capacitance (C q ). The present invention also relates to an electronic apparatus adapted to allow the tuning of its quantum capacitance.

First claim

The invention claimed is:

1. A system comprising an electronic apparatus, wherein the electronic apparatus comprises:
an electronic device comprising:
a gate electrode structure;
a dielectric structure arranged over said gate electrode structure; and
a charge sensing structure comprising at least one 2-dimensional charge sensing layer configured to sense at least one of electrical charges and electrical charge density changes induced by an external physical quantity, and that is configured and arranged over said dielectric structure to provide a gate capacitance between the charge sensing structure and the gate electrode structure; wherein said charge sensing structure shows a quantum capacitance in series with said gate capacitance resulting in a total capacitance between the charge sensing structure and the gate electrode structure;
a voltage detector electrically connected to the charge sensing structure or to the gate electrode structure, to detect an output voltage that is representative of said sensed electrical charges stored in said total capacitance;
wherein the system further comprises a mechanism configured and arranged to apply a gate voltage to said gate electrode structure, wherein said gate voltage is selected to, both:
make the electronic device operate around a most sensitive point of fermi level of the charge sensing structure; and
tune the quantum capacitance to modify a sensitivity and dynamic range of the electronic device.

2. The system according to claim 1 , wherein said mechanism comprises a voltage source that generates said gate voltage.

3. The system according to claim 1 , wherein said mechanism comprises a control unit configured and arranged to apply said gate voltage to said gate electrode structure, and to perform said selection of the gate voltage.

4. The system according to claim 3 , wherein said gate voltage is a DC voltage, an AC voltage, or a combination of DC and AC voltages, and wherein the control unit is configured to select the properties of said gate voltage, at least regarding its magnitude.

5. The system according to claim 3 , wherein the control unit comprises a selection input to receive selection signals regarding operation modes, and wherein the control unit is configured to select and apply said gate voltage to said gate electrode structure in response to a selection signal received through said selection input, to make the apparatus operate according to the selected operating mode.

6. The system according to claim 5 , wherein the control unit is configured not to apply said gate voltage to said gate electrode structure also in response to a selection signal received through said selection input.

7. The system according to claim 5 , wherein said operation modes include at least the following modes:
a high sensitive mode, in which the control unit does not apply said gate voltage to the gate electrode structure or selects and applies a gate voltage with an absolute magnitude below (0.9*Vt−Vcnp) volts, where Vt=qe·n*·A/Cg, where qe is the electron charge, n* the residual charge carrier density, A the area and Cg the capacitance of the gate and Vcnp the voltage at which the quantum capacitance is lowest, to reduce, not to increase or increase just a percentage below 35% said quantum capacitance;
a high dynamic range mode, in which the control unit selects and applies to the gate electrode structure a gate voltage with an absolute magnitude above (1.1*Vt−Vcnp) volts, to increase to a percentage above 45% said quantum capacitance; and
a trade-off mode, in which the control unit selects and applies to the gate electrode structure a gate voltage with an absolute magnitude between 0.9−(1.1*Vt−Vcnp) volts range, to increase said quantum capacitance to a percentage ranging between 35 and 45%.

8. The system according to claim 3 , wherein the control unit further comprises an adjustment input connected to an output of said voltage detector or of a read-out circuit operatively connected thereto, and is configured to implement a closed-loop adjustment process to adjust the gate voltage based on a detected output voltage or read-out signal received through said adjustment input.

9. The system according to claim 7 , wherein the control unit further comprises an adjustment input connected to an output of said voltage detector or of a read-out circuit operatively connected thereto, and is configured to implement a closed-loop adjustment process to adjust the gate voltage based on a detected output voltage or read-out signal received through said adjustment input, and wherein the control unit is configured to implement said closed-loop adjustment process also based on the selected operation mode.

10. The system according to claim 3 , wherein said voltage detector includes a reset circuit to discharge the total capacitance under the control of the control unit, and wherein the apparatus further comprises a read-out circuit operatively connected to the out of the voltage detector to provide a read-out signal based on the detected output voltage.

11. The system according to claim 1 , wherein the electronic device further comprises a sensitizing or functionalizing structure arranged over said charge sensing structure, wherein said sensitizing or functionalizing structure is configured to at least one of induce said electrical charge carriers and modify the charge carrier density therein induced by said external physical quantity, wherein the sensitizing or functionalizing structure is only sensitive to said external physical quantity.

12. The system according to claim 11 , wherein said sensitizing or functionalizing structure is a photoactive structure configured and arranged to, upon illumination, generate electron-hole pairs which, due to a field created by either a Schottky junction between the charge sensing structure and the photoactive structure or a topgate electrode on top of the photoactive structure or an interlayer between the charge sensing structure and the photoactive structure, are separated and either the electrons or holes gets transported, as said induced electrical charge carriers, to the charge sensing structure.

13. The system according to claim 12 , implementing an image sensor comprising an array of pixels, wherein the electronic apparatus comprises a plurality of said electronic devices each constituting one pixel of said array of pixels.

14. The system according to claim 1 , wherein the electronic device is absent of any sensitizing or functionalizing structure arranged over said charge sensing structure, the charge sensing structure being configured to at least one of induce itself said electrical charge carriers and modify the charge carrier density therein induced by said external physical quantity.

15. An electronic apparatus, comprising:
an electronic device comprising:
a gate electrode structure;
a dielectric structure arranged over said gate electrode structure; and
a charge sensing structure comprising at least one 2-dimensional charge sensing layer configured to sense at least one of electrical charges and electrical charge density changes induced by an external physical quantity, and that is configured and arranged over said dielectric structure to provide a gate capacitance between the charge sensing structure and the gate electrode structure, wherein said charge sensing structure shows a quantum capacitance in series with said gate capacitance resulting in a total capacitance between the charge sensing structure and the gate electrode structure;
a voltage detector electrically connected to the charge sensing structure or the gate electrode structure, t

Assignees

• Fundacio Inst De Ciencies Fotòniques
• Inst Catalana Recerca Estudis Avancats

Inventors

• Goossens Stijn
• Koppens Frank
• Konstantatos Gerasimos

Classifications

• H10F39/802

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10D86/80 Primary

  characterised by multiple passive components, e.g. resistors, capacitors or inductors · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• G01R15/16 Primary

  using capacitive devices · CPC title

• G01R29/24

  Arrangements for measuring quantities of charge · CPC title