Equalizer, operating method of equalizer and system including equalizer

Patent metadata

Field	Value
Publication number	US-11888656-B2
Application number	US-202217834262-A
Country	US
Kind code	B2
Filing date	Jun 7, 2022
Priority date	Jun 11, 2021
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.

First claim

What is claimed is:

1. An equalizer comprising:
an input amplifier configured to amplify and output an input signal;
a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and
a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2,
wherein the first arithmetic circuit is configured to perform weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals and output the weighted-summed received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals,
the second arithmetic circuit is configured to perform weighted summation of an output signal of the input amplifier, an output signal of the first arithmetic circuit, and the 2-1 feedback signal and output the weighted-summed output signal of the input amplifier, output signal of the first arithmetic circuit, and 2-1 feedback signal to the first sampling circuit,
the third arithmetic circuit configured to perform weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals and output the weighted-summed received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals, and
the fourth arithmetic circuit is configured to perform weighted summation of the output signal of the input amplifier, an output signal of the third arithmetic circuit, and the 1-1 feedback signal and output the weighted-summed output signal of the input amplifier, output signal of the third arithmetic circuit, and 1-1 feedback signal to the second sampling circuit.

2. The equalizer of claim 1 , wherein the first sampling circuit comprises:
a first sense amplifier configured to amplify an output signal of the second arithmetic circuit to generate the 1-1 feedback signal; and
a plurality of first latches configured to delay the 1-1 feedback signal to generate the 1-2 to 1-N feedback signals.

3. The equalizer of claim 1 , wherein the second sampling circuit comprises:
a first sense amplifier configured to amplify an output signal of the fourth arithmetic circuit to generate the 2-1 feedback signal; and
a plurality of second latches configured to delay the 2-1 feedback signal to generate the 2-2 to 2-M feedback signals.

4. The equalizer of claim 1 , wherein the first arithmetic circuit receives 1-α feedback signals, wherein a represents any even number greater than or equal to 2 and less than or equal to N and 2-b feedback signals, wherein b represents any odd number greater than 2 and less than or equal to M.

5. The equalizer of claim 4 , wherein
the second sampling circuit is configured to generate the 2-1 feedback signal based on a second clock signal,
the first sampling circuit is configured to generate the 1-α feedback signals based on the second clock signal, and
the second sampling circuit is further configured to generate the 2-b feedback signals based on the second clock signal.

6. The equalizer of claim 4 , wherein the first arithmetic circuit comprises:
a plurality of first multipliers configured to multiply each of the 1-α feedback signals and the 2-b feedback signals by a coefficient; and
a first summer configured to sum output values of the plurality of first multipliers.

7. The equalizer of claim 1 , wherein the second arithmetic circuit comprises:
a plurality of second multipliers configured to multiply each of the output signal of the first arithmetic circuit and the 2-1 feedback signal by a coefficient; and
a second summer configured to sum the output signal of the input amplifier and output values of the plurality of second multipliers.

8. The equalizer of claim 7 , wherein the second summer is connected to an output node of the input amplifier, an output node of the plurality of second multipliers, and an input node of the first sampling circuit.

9. The equalizer of claim 1 , wherein the third arithmetic circuit is configured to:
perform weighted summation of
1-c feedback signals, wherein c represents any odd number greater than 2 and less than or equal to N, and
2-d feedback signals, wherein d represents any even number greater than or equal to 2 and less than or equal to M, and

output the weighted-summed 1-c feedback signals and 2-d feedback signals.

10. The equalizer of claim 9 , wherein
the first sampling circuit is configured to generate the 1-1 feedback signal and the 1-c feedback signals based on a first clock signal, and
the second sampling circuit is configured to generate the 2-d feedback signals based on the first clock signal.

11. The equalizer of claim 9 , wherein the third arithmetic circuit comprises:
a plurality of third multipliers configured to multiply each of the 1-c feedback signals and the 2-d feedback signals by a coefficient; and
a third summer configured to sum output values of the plurality of third multipliers.

12. The equalizer of claim 1 , wherein the fourth arithmetic circuit comprises:
a plurality of fourth multipliers configured to multiply each of the output signal of the third arithmetic circuit and the 1-1 feedback signal by a coefficient; and
a fourth summer configured to sum the output signal of the input amplifier and output values of the plurality of fourth multipliers.

13. The equalizer of claim 12 , wherein the fourth summer is connected to an output node of the input amplifier, an output node of the plurality of fourth multipliers, and an input node of the second sampling circuit.

14. The equalizer of claim 1 , wherein
the first equalization circuit and the second equalization circuit are configured to receive a clock signal,
the first equalization circuit is configured to operate at a first edge of the clock signal, and
the second equalization circuit is configured to operate at a second edge of the clock signal.

15. An operating method of an equalizer, the operating method comprising:
amplifying an input signal through an input amplifier;
generating 1-1 to 1-N feedback signals through a first sampling circuit, wherein N is a natural number greater than or equal to 2;
generating 2-1 to 2-M feedback signals through a second sampling circuit, wherein M is a natural number greater than or equal to 2;
performing, through a first arithmetic circuit, weighted summation of received feedback signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals;
performing, through a third arithmetic circuit, weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals;
performing, through a second arithmetic circuit, weighted summation of an output signal of the input amplifier, an output signal of the first arithmetic circuit, and the 2-1 feedback signal, and outputting the weighted-summed output signal of the input amplifier, output signal of the first arithmetic circuit, and 2-1 feedback signal to the first sampling circuit; and
performing, through a fourth arithmetic circuit, weighted summation of the output signal of the input amplifier, an output signal of the third arithmetic circuit, and the 1-1 feedback signal and outputting the weighted-summed output signal of the input amplifier,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Kyeongjoon
• Kim Hanseok
• Park Jaehyun
• Bae Junhan
• Song Gyeongseok
• Ryu Jongjae

Classifications

• H04L25/03267 Primary

  with decision feedback equalisers · CPC title

• H04L25/03121

  using a two-tap delay line · CPC title

• H04L25/03146 Primary

  with a recursive structure (H04L25/03127 takes precedence) · CPC title

• H04L2025/0349

  as a feedback filter · CPC title

• H04L25/03114

  non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals · CPC title