Decision feedback equalizer

Patent metadata

Field	Value
Publication number	US-8953669-B2
Application number	US-201213981914-A
Country	US
Kind code	B2
Filing date	Jan 24, 2012
Priority date	Jan 26, 2011
Publication date	Feb 10, 2015
Grant date	Feb 10, 2015

Abstract

A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21 , coefficient units Tap 1 a , Tap 2 to Tapn) that sums an input signal to weighted versions of feedback signals FB 1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L 2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB 2 to FBn. The decision feedback equalizer includes a decision circuit 12 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of decision as feedback signal FB 1 . The second decision circuit operates in synchronism with the clock signal.

First claim

The invention claimed is:

1. A decision feedback equalizer, comprising:
a first weighting addition circuit that adds an input signal and weighted versions of first to nth feedback signals together, n being an integer not less than 2;
a first decision circuit that decides whether or not the result of addition by the first weighting addition circuit is at least a defined threshold value and that outputs the decision to a shift register, the first decision circuit operating in synchronism with a clock signal;
the shift register sequentially holding the decision output by the first decision circuit in synchronism with the clock signal, the shift register outputting contents held by component registers thereof as the second to nth feedback signals, respectively; and
a second decision circuit that decides whether or not the result of the addition by the first weighting addition circuit is at least a defined threshold value and that outputs the decision as the first feedback signal, the second decision circuit operating in synchronism with the clock signal.

2. The decision feedback equalizer according to claim 1 , wherein
the second decision circuit is constructed with circuit constants different from those of the first decision circuit so that the second decision circuit will operate at a speed faster than the first decision circuit.

3. The decision feedback equalizer according to claim 2 , wherein
at least some of transistors of the second decision circuit are of a size smaller than transistors of the first decision circuit.

4. The decision feedback equalizer according to claim 3 , wherein
the first decision circuit and the second decision circuit each include a data holding part that holds the result of the addition and that is operated by the clock signal;
a transistor of the data holding part of the second decision circuit being smaller in size than a transistor of the data holding part of the first decision circuit.

5. The decision feedback equalizer according to claim 2 , wherein
the second decision circuit operates with a logical amplitude less than that of the first decision circuit.

6. The decision feedback equalizer according to claim 2 , wherein
the first decision circuit and the second decision circuit each include a data holding part that holds the result of the addition and that operates with the clock signal;
a load resistor of the data holding part of the second decision circuit being lower in a resistance value than that of a load resistor of the data holding part of the first decision circuit.

7. The decision feedback equalizer according to claim 1 , further comprising:
a weighting circuit applying to the result of decision by the first decision circuit a weighting equivalent to a weighting applied to the first feedback signal;
the first weighting addition circuit further adding an output signal of the weighting circuit;
control being managed so as to supply power exclusively to the weighting circuit or to both the second decision circuit and a weighting function for the first feedback signal.

8. A decision feedback equalizer, comprising:
a first weighting addition circuit that adds an input signal and weighted versions of first to nth feedback signals together, n being an integer not less than 2;
a first decision circuit that decides whether or not the result of addition by the first weighting addition circuit is at least a defined threshold value and that outputs the decision to a shift register, the first decision circuit operating in synchronism with a clock signal;
the shift register sequentially holding the decision output by the first decision circuit in synchronism with the clock signal, the shift register outputting contents held by component registers thereof as the second to nth feedback signals, respectively;
a second weighting addition circuit that adds together the input signal and weighted versions of the first to nth feedback signals, respectively; and
a second decision circuit that decides whether or not the result of addition by the second weighting addition circuit is at least a defined threshold value and that outputs the decision as the first feedback signal, the second decision circuit operating in synchronism with the clock signal.

9. The decision feedback equalizer according to claim 8 , wherein
a transistor of the second weighting addition circuit is smaller in size than a transistor of the first weighting addition circuit.

10. A decision feedback equalizer, comprising:
a first weighting addition circuit that adds an input signal and weighted versions of second to nth feedback signals together, n being an integer not less than 2, without adding a weighted version of a first feedback signal of the n feedback signals;
a first decision circuit that decides whether or not the result of addition by the first weighting addition circuit is at least a defined threshold value and that outputs the decision to a shift register, the first decision circuit operating in synchronism with a clock signal;
the shift register sequentially holding the decision output by the first decision circuit in synchronism with the clock signal, the shift register outputting contents held by component registers thereof as the second to nth feedback signals, respectively; and
a second decision circuit that decides whether or not the result of the addition by the first weighting addition circuit is at least a defined threshold value and that outputs the decision as the first feedback signal, the second decision circuit operating in synchronism with the clock signal,
wherein the first decision circuit is configured so that the defined threshold value for the first decision circuit is controllable by the weighted version of the first feedback signal.

11. The decision feedback equalizer according to claim 10 , wherein,
the second decision circuit is configured so that the defined threshold value for the second decision circuit is controllable by the weighted version of the first feedback signal.

12. A receiver including the decision feedback equalizer according to claim 1 .

13. A communication system including the receiver according to claim 12 and a transmitter configured for sending out a transmission signal to the receiver.

14. A semiconductor device including at least one receiver according to claim 12 .

Assignees

• Amamiya Yasushi
• Renesas Electronics Corp

Inventors

• Amamiya Yasushi

Classifications

• H04B3/06 Primary

  by the transmitted signal · CPC title

• H04B7/005 Primary

  Control of transmission; Equalising · CPC title

• H04L25/03267 Primary

  with decision feedback equalisers · CPC title

• H04L25/03197

  methods of calculation involving metrics · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title