Analog multiplexer circuit and analog-digital conversion system

Patent metadata

Field	Value
Publication number	US-11888495-B2
Application number	US-201917768168-A
Country	US
Kind code	B2
Filing date	Oct 23, 2019
Priority date	Oct 23, 2019
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).

First claim

The invention claimed is:

1. An analog demultiplexer circuit comprising:
a clock distribution circuit configured to output first clock signals and second clock signals complementary thereto;
a first track-and-hold circuit configured to hold analog input signals in synchronization with the first clock signals; and
a second track-and-hold circuit configured to hold the analog input signals in synchronization with the second clock signals.

2. The analog demultiplexer circuit according to claim 1 , further comprising:
a first addition circuit configured to add first output signals of the first track-and-hold circuit and second output signals of the second track-and-hold circuit; and
a subtraction circuit configured to subtract the second output signals of the second track-and-hold circuits from the first output signals of the first track-and-hold circuit.

3. The analog demultiplexer circuit according to claim 2 , wherein the analog demultiplexer circuit is comprised in an analog-to-digital conversion system, the analog-to-digital conversion system comprising:
a first analog-to-digital converter configured to convert a first analog output signal output from the first addition circuit of the analog demultiplexer circuit into a first digital signal;
a second analog-to-digital converter configured to convert a second analog output signal output from the subtraction circuit of the analog demultiplexer circuit into a second digital signal;
a folding processor configured to execute a folding processing of a third output signal of the second analog-to-digital converter with a frequency of ½ of the first clock signals as a boundary; and
a second addition circuit configured to add a fourth output signal of the first analog-to-digital converter and a fifth output signal of the folding processor.

4. The analog-to-digital conversion system according to claim 3 , wherein
the folding processor is configured to performs intensity compensation so that an intensity of a signal after the folding processing is the same as an intensity of the fourth output signal of the first analog-to-digital converter.

5. The analog demultiplexer circuit according to claim 1 , further comprising:
a differential input/differential output type first addition circuit configured to add first output signals of the first track-and-hold circuit and second output signals of the second track-and-hold circuit; and
a differential input/differential output type second addition circuit configured to add the first output signals of the first track-and-hold circuit and the second output signals of the second track-and-hold circuit, wherein
the clock distribution circuit outputs the first clock signals and the second clock signals in the form of respective differential signals;
the first track-and-hold circuit and the second track-and-hold circuit are differential input/differential output type circuits;
the differential input/differential output type first addition circuit is configured to add a first positive-phase-side output signal of the first track-and-hold circuit and a second positive-phase-side output signal of the second track-and-hold circuit, and adds a first negative-phase-side output signal of the first track-and-hold circuit and a second negative-phase-side output signal of the second track-and-hold circuit; and
the differential input/differential output type second addition circuit is configured to add the first positive-phase-side output signal of the first track-and-hold circuit and the second negative-phase-side output signal of the second track-and-hold circuit, and adds the first negative-phase-side output signal of the first track-and-hold circuit and the second positive-phase-side output signal of the second track-and-hold circuit.

6. The analog demultiplexer circuit according to claim 5 , wherein the analog demultiplexer circuit is comprised in an analog-to-digital conversion system, the analog-to-digital conversion system comprising:
a first differential input type analog-to-digital converter configured to convert a first analog output signal output from the differential input/differential output type first addition circuit of the analog demultiplexer circuit into a first digital signal;
a second differential input type analog-to-digital converter configured to convert a second analog output signal output from the differential input/differential output type second addition circuit of the analog demultiplexer circuit into a second digital signal;
a folding processor configured to execute a folding processing of a third output signal of the second differential input type analog-to-digital converter with a frequency of ½ of the first clock signals as a boundary; and
a third addition circuit configured to add a fourth output signal of the first differential input type analog-to-digital converter and a fifth output signal of the folding processor.

7. The analog-to-digital conversion system according to claim 6 , wherein
the folding processor is configured to performs intensity compensation so that an intensity of a signal after the folding processing is the same as an intensity of the fourth output signal of the first differential input type analog-to-digital converter.

8. An analog-to-digital conversion system comprising:
a analog demultiplexer circuit, comprising:
a clock distribution circuit configured to output first clock signals and second clock signals complementary thereto;
a first track-and-hold circuit configured to hold analog input signals in synchronization with the first clock signals; and
a second track-and-hold circuit configured to hold the analog input signals in synchronization with the second clock signals;

a first analog-to-digital converter configured to convert a first analog output signal output from the first track-and-hold circuit of the analog demultiplexer circuit into a first digital signal;
a second analog-to-digital converter configured to convert a second analog output signal output from the second track-and-hold circuit of the analog demultiplexer circuit into a second digital signal;
a first addition circuit configured to add a first output signal of the first analog-to-digital converter and a second output signal of the second analog-to-digital converter;
a subtraction circuit configured to subtract the second output signal of the second analog-to-digital converter from the first output signal of the first analog-to-digital converter;
a folding processor configured to execute a folding processing of a third output signal of the subtraction circuit with a frequency of ½ of the first clock signals as a boundary; and
a second addition circuit configured to add a fourth output signal of the first addition circuit and a sixth output signal of the folding processor.

9. The analog-to-digital conversion system according to claim 8 , wherein
the folding processor is configured to performs intensity compensation so that an intensity of a signal after the folding processing is the same as an intensity of the fourth output signal of the first addition circuit.

Assignees

• Nippon Telegraph & Telephone

Inventors

• Nagatani Munehiko
• Jo Teruo
• Yamazaki Hiroshi
• Nosaka Hideyuki

Classifications

• H03M1/1255 Primary

  Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03M1/1295

  Clamping, i.e. adjusting the DC level of the input signal to a predetermined value · CPC title

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title