Integrated circuit, method for synchronizing clocks therefor and electronic device

Patent metadata

Field	Value
Publication number	US-11888488-B2
Application number	US-202117515233-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Dec 2, 2020
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a clock source configured to generate a clock signal of the integrated circuit;
at least two functional circuits; and
at least two clock generators corresponding to the at least two functional circuits, wherein each of the clock generators is electrically coupled to the clock source and electrically coupled to a corresponding functional circuit, and is configured to:
generate a clock signal of the corresponding functional circuit based on the clock signal of the integrated circuit and an initial phase of the corresponding functional circuit, so as to keep clock signals of all the functional circuits synchronized,
wherein the initial phase of the corresponding functional circuit is determined based on a clock delay of a reference circuit and a clock delay of the corresponding functional circuit, and the reference circuit is one of the at least two functional circuits; and the clock delay of the corresponding functional circuit is determined based on a transmission distance, over which the clock signal of the integrated circuit is transmitted from the clock source to the corresponding functional circuit, and a load of the corresponding functional circuit.

2. The integrated circuit according to claim 1 , further comprising a control circuit, which is configured to:
determine, for each of the functional circuits, the clock delay of the functional circuit based on a transmission distance, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuit, and a load of the functional circuit;
determine, for each of the functional circuits other than the reference circuit, an initial phase of the functional circuit based on a clock delay of the reference circuit and a clock delay of the functional circuit; and
send an initial phase of each of the functional circuits to a clock generator corresponding to the functional circuit to generate the clock signal of the functional circuit.

3. The integrated circuit according to claim 2 , wherein the clock signal of the integrated circuit includes K clock pulses, and K is an integer greater than 1;
if a clock delay of an i th functional circuit is smaller than or equal to the clock delay of the reference circuit, an initial phase INV i of the i th functional circuit satisfies: INV i =(Ø 0 −Ø i )/Δ; and
if the clock delay of the i th functional circuit is greater than the clock delay of the reference circuit, the initial phase INV i of the i th functional circuit satisfies: INV i =K+(Ø 0 −Ø i )/Δ,
wherein Ø 0 represents the clock delay of the reference circuit, Ø i represents the clock delay of the i th functional circuit, Δ represents a phase difference between two adjacent clock pulses, and i is a positive integer not greater than a total number of the at least two functional circuits.

4. The integrated circuit according to claim 3 , wherein K is equal to an integer power of 2.

5. The integrated circuit according to claim 2 , wherein the reference circuit is a functional circuit with a maximum clock delay among the at least two functional circuits.

6. The integrated circuit according to claim 2 , wherein each of the functional circuits is configured to: update the clock delay of the functional circuit based on a current load state of the functional circuit; and
the control circuit is further configured to:
update the initial phase of each of the functional circuits based on an updated clock delay of the functional circuit; and
send an updated initial phase of each of the functional circuits to the clock generator corresponding to the functional circuit, so as to generate an updated clock signal of the functional circuit.

7. The integrated circuit according to claim 1 , wherein the clock generators are clock generators based on time-average-frequency direct period synthesis; and clock signals of the functional circuits are generated based on the clock signal of the integrated circuit, control words of the clock generators and initial phases of the functional circuits.

8. The integrated circuit according to claim 7 , further comprising a control circuit, which is configured to:
send the acquired control words to each of the clock generators, respectively.

9. The integrated circuit according to claim 1 , wherein the clock source is implemented in one of the following forms:
a Johnson counter; and
a plurality of cross-coupled NAND gates.

10. The integrated circuit according to claim 1 , further comprising a newly-added functional circuit and a corresponding newly-added clock generator, wherein the newly-added clock generator is configured to:
determine an initial phase of the newly-added functional circuit; and
generate a clock signal of the newly-added functional circuit based on the clock signal of the integrated circuit and the initial phase of the newly-added functional circuit, so as to keep the clock signal of the newly-added functional circuit and clock signals of other functional circuits synchronized;
wherein the initial phase is determined based on a transmission distance, over which the clock signal of the integrated circuit is transmitted from the clock source to the newly-added functional circuit, and a load of the newly-added functional circuit.

11. The integrated circuit according to claim 4 , wherein the reference circuit is a functional circuit with a maximum clock delay among the at least two functional circuits; the clock source is implemented in one of the following forms: a Johnson counter, and a plurality of cross-coupled NAND gates;
the clock generators are clock generators based on time-average-frequency direct period synthesis; and clock signals of the functional circuits are generated based on the clock signal of the integrated circuit, control words of the clock generators and initial phases of the functional circuits; and the control circuit is further configured to: send the acquired control words to each of the clock generators, respectively;
the functional circuits are configured to: update the clock delay of the functional circuit based on a current load state of the functional circuit; and
the control circuit is further configured to: update the initial phase of each of the functional circuits based on an updated clock delay of the functional circuit; and send an updated initial phase of each of the functional circuits to the clock generator corresponding to the functional circuit, so as to generate an updated clock signal of the functional circuit.

12. A method for synchronizing clocks for an integrated circuit, wherein the integrated circuit comprises a clock source, at least two functional circuits, and at least two clock generators corresponding to the at least two functional circuits; and the method comprises:
generating, by the clock source, a clock signal of the integrated circuit;
determining a clock delay of a corresponding functional circuit based on a transmission distance, over which the clock signal of the integrated circuit is transmitted from the clock source to the corresponding functional circuit, and a load of the corresponding functional circuit; and
determining an initial phase of the corresponding functional circuit based on a clock delay of a reference circuit and the clock delay of the corresponding functional circuit, wherein the reference circuit is one of the at least two functional circuits; and
generating, by each of the clock generators, a clock signal of the corresponding functional circuit based on the clock signal of the integrated circuit and the initial phase of the corresponding functional circuit, so as to keep clock signals of all the

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Xiu Liming

Classifications

• H03L7/00 Primary

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K23/542

  with crossed-couplings, i.e. Johnson counters · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title