Clock-controlled circuitry

Patent metadata

Field	Value
Publication number	US-10564666-B2
Application number	US-201916366907-A
Country	US
Kind code	B2
Filing date	Mar 27, 2019
Priority date	Mar 29, 2018
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

Clock-controlled circuitry organised into at least first and second clock domains, the first clock domain configured to operate based on a first clock signal and the second clock domain configured to operate based on a second clock signal, wherein: the first clock domain comprises a first signal generator operable to generate a first repetitive signal synchronised to the first clock signal; the second clock domain comprises a second signal generator operable to generate a second repetitive signal synchronised to the second clock signal; the first signal generator is operable, when operating in master mode, to output to the second signal generator a first synchronisation signal indicative of a phase of the first repetitive signal; and the second signal generator is operable, when operating in slave mode, to: set a timing of the second repetitive signal relative to the second clock signal based on the first synchronisation signal so that the second repetitive signal is set to have a phase relationship with the first repetitive signal which then meets a slave specification; and re-set the timing of the second repetitive signal relative to the second clock signal if it is determined that the phase relationship has changed such that it no longer meets the slave specification.

First claim

The invention claimed is:

1. Clock-controlled circuitry organised into at least first and second clock domains, the first clock domain configured to operate based on a first clock signal and the second clock domain configured to operate based on a second clock signal, wherein:
the first clock domain comprises a first signal generator operable to generate a first repetitive signal synchronised to the first clock signal;
the second clock domain comprises a second signal generator operable to generate a second repetitive signal synchronised to the second clock signal;
the first signal generator is operable, when operating in master mode, to output to the second signal generator a first synchronisation signal indicative of a phase of the first repetitive signal; and
the second signal generator is operable, when operating in slave mode, to:
set a timing of the second repetitive signal relative to the second clock signal based on the first synchronisation signal so that the second repetitive signal is set to have a phase relationship with the first repetitive signal which then meets a slave specification; and
re-set the timing of the second repetitive signal relative to the second clock signal if it is determined that the phase relationship has changed such that it no longer meets the slave specification.

2. The clock-controlled circuitry as claimed in claim 1 , wherein the second signal generator is operable to re-set the timing of the second repetitive signal relative to the second clock signal based on the first synchronisation signal so that the second repetitive signal is again set to have a phase relationship with the first repetitive signal which then meets the slave specification.

3. The clock-controlled circuitry as claimed in claim 1 , wherein the second signal generator, or another signal generator of the clock-controlled circuitry, is operable to monitor the phase relationship between the second repetitive signal and the first repetitive signal after the timing of the second repetitive signal relative to the second clock signal has been set and to determine if that phase relationship has changed such that it no longer meets the slave specification optionally wherein the second signal generator or the other signal generator is operable to monitor the phase relationship between the second repetitive signal and the first repetitive signal by monitoring a phase relationship between the second repetitive signal and the first synchronisation signal.

4. The clock-controlled circuitry as claimed in claim 3 , wherein the second signal generator or the other signal generator is operable to monitor the phase relationship between the second repetitive signal and the first repetitive signal by monitoring a phase relationship between the second repetitive signal and a retimed first synchronisation signal being a retimed version of the first synchronisation signal.

5. The clock-controlled circuitry as claimed in claim 4 , wherein the second signal generator or the other signal generator is operable to monitor the phase relationship between the second repetitive signal and the first repetitive signal by obtaining a count value indicative of the phase relationship by:
incrementing a counter between corresponding edges of the second repetitive signal and the first synchronisation signal or retimed first synchronisation signal; or
incrementing a counter while the second repetitive signal and the first synchronisation signal or retimed first synchronisation signal have the same value as one another; or
incrementing a counter while the second repetitive signal and the first synchronisation signal or retimed first synchronisation signal have different values from one another.

6. The clock-controlled circuitry as claimed in claim 1 , wherein:
the first synchronisation signal is part or all of the first repetitive signal, or is derived from the first repetitive signal; or
the second signal generator is operable when operating in slave mode, to receive a release signal, and, if the release signal is received, to transition its operation to free-running mode, and in connection with the transition to free-running mode, to continue generation of the second repetitive signal at its existing timing relative to the second clock signal without taking account of the phase relationship between the second repetitive signal and the first repetitive signal.

7. The clock-controlled circuitry as claimed in claim 1 , wherein the second signal generator is operable:
when operating in slave mode, to receive a re-synch signal indicating a change in the first repetitive signal, and, if the re-synch signal is received, to re-set the timing of the second repetitive signal relative to the second clock signal, optionally wherein the re-synch signal indicates a change in a repeating pattern of the first repetitive signal, and the second signal generator is operable, if the re-synch signal is received, to re-set the timing of the second repetitive signal relative to the second clock signal based on the re-synch signal and re-configure the second repetitive signal based on the change in the repeating pattern indicated by the re-synch signal.

8. The clock-controlled circuitry as claimed in claim 1 , wherein the second signal generator is operable, when operating in slave mode, to monitor operation of the first signal generator, and, if the first signal generator is determined to become disabled, to:
transition its operation to master mode; and then
continue generation of the second repetitive signal at its existing timing relative to the second clock signal without taking account of the phase relationship between the second repetitive signal and the first repetitive signal, and output a second synchronisation signal indicative of a phase of the second repetitive signal.

9. The clock-controlled circuitry as claimed in claim 8 , wherein the first signal generator is operable, when re-enabled after being disabled, to:
monitor operation of the second signal generator and determine if the second clock control circuit is operating in master mode; and
when it is determined that the second clock control circuit is operating in master mode, operate in slave mode.

10. The clock-controlled circuitry as claimed in claim 9 , wherein the first signal generator is operable, when operating in slave mode, to:
set a timing of the first repetitive signal relative to the first clock signal based on the second synchronisation signal so that the first repetitive signal is set to have a phase relationship with the second repetitive signal which then meets the slave specification; and
re-set the timing of the first repetitive signal relative to the first clock signal if it is determined that that phase relationship has changed such that it no longer meets the slave specification, optionally wherein the first signal generator is operable to re-set the timing of the first repetitive signal relative to the first clock signal based on the second synchronisation signal so that the first repetitive signal is again set to have a phase relationship with the second repetitive signal which then meets the slave specification.

11. The clock-controlled circuitry as claimed in claim 10 , wherein the first signal generator, or another signal generator of the clock-controlled circuitry, is operable to monitor the phase relationship between the first repetitive signal and the second repetitive signal after the timing of the first repetitive signal relative to the first clock signal has been set and to determine if that phase relationship has changed such that it no longer meets the slave specification.

12. The clock-controlled circuitry as claimed in

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Morgan Ross
• Nalage Shantanu Shrikant

Classifications

• H04R3/00

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K21/08

  Output circuits · CPC title