Interconnect structures and methods of fabrication

Patent metadata

Field	Value
Publication number	US-11887887-B2
Application number	US-202217850876-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Sep 27, 2019
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

First claim

What is claimed is:

1. An integrated circuit (IC) interconnect structure, comprising:
a first dielectric material layer adjacent to at least a portion of a first interconnect feature;
a second interconnect feature in contact with at least a portion of the first interconnect feature;
a second dielectric material layer adjacent to at least a portion of the second interconnect feature;
a third dielectric material layer between the first and second dielectric material layers, wherein the third dielectric material layer is adjacent to the first interconnect feature and in contact with a portion of the second interconnect feature, and wherein the third dielectric material layer has a greater nitrogen content than at least the first dielectric material layer and wherein the third dielectric material layer comprises carbon; and
a fourth dielectric material layer between the second and third dielectric material layers, wherein the fourth dielectric material layer is adjacent to the second interconnect feature and in contact with a portion of the first interconnect feature, wherein the fourth dielectric material layer has a greater nitrogen content than at least the second dielectric material layer, and wherein the fourth dielectric material layer comprises carbon, and wherein carbon content within the third dielectric material layer decreases with proximity to the fourth dielectric material layer and wherein carbon content within the fourth dielectric material layer decreases with proximity to the third dielectric material layer.

2. The IC interconnect structure of claim 1 , wherein the third dielectric material layer further comprises silicon, and oxygen.

3. The IC interconnect structure of claim 2 , wherein the third or fourth dielectric material layer has a maximum carbon concentration of at least 2 at. %.

4. The IC interconnect structure of claim 2 , wherein the first dielectric material layer comprises silicon and oxygen.

5. The IC interconnect structure of claim 1 , wherein carbon content in the first and second dielectric material layers is substantially zero.

6. The IC interconnect structure of claim 1 , wherein:
the carbon content within the third dielectric material layer has a minimum less than 0.05 at. %; and
the carbon content within the fourth dielectric material layer has a minimum less than 0.05 at. %.

7. The IC interconnect structure of claim 1 , wherein:
the third dielectric material layer further comprises silicon, and oxygen; and
the fourth dielectric material layer further comprises silicon and oxygen.

8. The IC interconnect structure of claim 1 , wherein:
the first dielectric material layer comprises silicon and oxygen; and
the second dielectric material layer comprises silicon and oxygen.

9. The IC interconnect structure of claim 1 , wherein:
the carbon content within the third dielectric material has a maximum of at least 2 at. %; and
the carbon content within the fourth dielectric material layer has a maximum of at least 2 at. %.

10. The IC interconnect structure of claim 1 , wherein the first interconnect feature comprises a wide upper portion and a narrow lower portion, wherein the second interconnect feature comprises a narrow upper portion and wide lower portion and wherein the wide upper portion of the first interconnect feature is in contact with the wide lower portion of the second interconnect feature.

11. The IC interconnect structure of claim 10 , wherein the first interconnect feature is within a first metallization level further comprising a third interconnect feature adjacent to the first dielectric material layer and spatially distant from the first interconnect feature, and wherein the third interconnect feature has an uppermost surface that is substantially coplanar with the uppermost surface of the first interconnect feature.

12. The IC interconnect structure of claim 11 , wherein the second interconnect feature is within a second metallization level further comprising a fourth interconnect feature adjacent to the second dielectric material layer and spatially distant from the second interconnect feature, and wherein the fourth interconnect feature has a lowermost surface that is substantially coplanar with the lowermost surface of the second interconnect feature, and wherein the uppermost surface of the third interconnect feature is in contact with a portion of the lowermost surface of the fourth interconnect feature.

13. The IC interconnect structure of claim 12 , wherein the third interconnect feature is spatially distant from the first interconnect feature by an amount that is substantially equal to an amount the fourth interconnect feature is spatially distant from the second interconnect feature.

14. A system comprising:
a processor comprising:
a transistor comprising:
a drain contact coupled to a drain;
a source contact coupled to a source; and
a gate contact coupled to a gate; and

an IC interconnect structure coupled with the transistor, wherein the IC interconnect structure comprises:
a first dielectric material layer adjacent to at least a portion of a first interconnect feature;
a second interconnect feature in contact with at least a portion of the first interconnect feature;
a second dielectric material layer adjacent to at least a portion of the second interconnect feature;
a third dielectric material layer between the first and second dielectric material layers, wherein the third dielectric material layer is adjacent to the first interconnect feature and in contact with a portion of the second interconnect feature, and wherein the third dielectric material layer has a greater nitrogen content than at least the first dielectric material layer and wherein the third dielectric material layer comprises carbon; and
a fourth dielectric material layer between the second and third dielectric material layers, wherein the fourth dielectric material layer is adjacent to the second interconnect feature and in contact with a portion of the first interconnect feature, wherein the fourth dielectric material layer has a greater nitrogen content than at least the second dielectric material layer, wherein the fourth dielectric material layer comprises carbon, wherein carbon content within the third dielectric material layer decreases with proximity to the second interconnect feature, and wherein carbon content within the fourth dielectric material layer decreases with proximity to the first interconnect feature; and

a power supply comprising an output coupled to the processor.

15. The system of claim 14 , further comprising a battery coupled to an input of the power supply.

16. A method of fabricating an integrated circuit interconnect structure, the method
comprising:
preparing a first substrate, the preparing comprising:
forming a material layer stack comprising a first dielectric material layer and a second dielectric material layer on the first dielectric material layer, wherein the second
dielectric material layer comprises more nitrogen than the first dielectric material layer, and further comprises carbon;

forming a first opening in the material layer stack;
depositing a first conductive material in the first opening; and
forming a first interconnect feature by planarizing the first conductive material and an upper portion of the second dielectric material layer to form a first interconnect feature;

preparing a second substrate, the preparing comprising:
forming a second opening in a third dielectric material layer and an underlying fourth dielectric material layer, wherein the third dielectric material layer compri

Assignees

• Intel Corp

Inventors

• Chandhok Manish
• Chebiam Ramanan
• Mueller Brennen
• Carver Colin
• Bielefeld Jeffery
• Kabir Nafees
• Vreeland Richard
• Brezinski William

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/093

  by modifying materials of the dielectric parts · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title