Semiconductor package structure having substrate with embedded electronic component and conductive pillars

Patent metadata

Field	Value
Publication number	US-11881448-B2
Application number	US-202117315067-A
Country	US
Kind code	B2
Filing date	May 7, 2021
Priority date	May 7, 2021
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first package and a second package. The first package includes a first substrate, an electronic component, a trace layer, and a first conductive structure. The first substrate has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the first substrate. The trace layer has an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate. The first conductive structure electrically connects the trace layer to the second surface of the first substrate. The second package is disposed on the first surface of the first substrate of the first package.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a first package, comprising:
a first substrate having a first surface and a second surface opposite to the first surface;
an electronic component embedded in the first substrate;
a trace layer having an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate, wherein the trace layer comprises a first portion within a vertical projection area of the electronic component and a second portion outside of the vertical projection area of the electronic component;
a first conductive structure embedded in the first substrate and connecting the second portion of the trace layer to the second surface of the first substrate; and
a dielectric layer contacting the first surface of the first substrate and exposing the first portion of the trace layer,
wherein the dielectric layer has an opening exposing the first portion of the trace layer, and the semiconductor package structure further comprises a solder extending into the opening.

2. A semiconductor package structure, comprising:
a first package, comprising:
a first substrate having a first surface and a second surface opposite to the first surface;
an electronic component embedded in the first substrate;
a trace layer having an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate, wherein the trace layer comprises a first portion within a vertical projection area of the electronic component and a second portion outside of the vertical projection area of the electronic component; and
a first conductive structure embedded in the first substrate and connecting the second portion of the trace layer to the second surface of the first substrate,
wherein the first conductive structure comprises a pillar connected to the second portion of the trace layer, and a central axis of the pillar is misaligned with a central axis of the second portion of the trace layer in a vertical direction.

3. The semiconductor package structure of claim 2 , wherein the first substrate comprises a first portion between the first portion of the trace layer and the second portion of the trace layer.

4. The semiconductor package structure of claim 3 , wherein the trace layer further comprises a third portion outside of the vertical projection area of the electronic component, and wherein in a cross-sectional view perspective, the third portion of the trace layer is spaced apart from the second portion of the trace layer and the first portion of the trace layer, and a width of the third portion of the trace layer is less than a width of the second portion of the trace layer.

5. The semiconductor package structure of claim 4 , wherein the third portion of the trace layer has a first surface and a second surface opposite to the first surface, the first surface of the third portion of the trace layer is substantially aligned with the first surface of the first substrate, and the first substrate further comprises a second portion contacting the entire second surface of the third portion of the trace layer.

6. The semiconductor package structure of claim 4 , wherein the third portion of the trace layer is spaced apart from the second portion of the trace layer by a second portion of the first substrate.

7. The semiconductor package structure of claim 4 , wherein there is free of any solder over the third portion of the trace layer.

8. The semiconductor package structure of claim 2 , further comprising a dielectric layer contacting the first surface of the first substrate and exposing the first portion of the trace layer.

9. The semiconductor package structure of claim 8 , wherein the trace layer further comprises a third portion outside of the vertical projection area of the electronic component, and wherein in a cross-sectional view perspective, the third portion of the trace layer is spaced apart from the second portion of the trace layer and the first portion of the trace layer, a first surface of the third portion of the trace layer is substantially aligned with the first surface of the first substrate, and the dielectric layer contacts the entire first surface of the third portion of the trace layer.

10. A semiconductor package structure, comprising:
a first package, comprising:
a first substrate having a first surface and a second surface opposite to the first surface;
a trace layer embedded in the first substrate and proximal to the first surface of the first substrate;
a first conductive pillar connected to the trace layer; and
a first conductive via connecting the first conductive pillar to the second surface of the first substrate, wherein the first conductive via and the first conductive pillar are within a same layer of the first substrate;

a second package disposed on the first surface of the first substrate of the first package; and
a conductive layer below the first conductive via, and a thickness of the conductive layer is less than a thickness of the trace layer.

11. The semiconductor package structure of claim 10 , further comprising an electronic component embedded in the first substrate and under a first portion of the trace layer.

12. The semiconductor package structure of claim 11 , wherein the electronic component has an active surface facing the trace layer, and the first substrate comprises a portion extending between the trace layer and the active surface of the electronic component.

13. The semiconductor package structure of claim 12 , further comprising a second electronic component embedded in the first substrate and under a second portion of the trace layer, wherein the second portion of the trace layer is spaced apart from the first portion of the trace layer.

14. The semiconductor package structure of claim 13 , wherein the second electronic component has an active surface facing away from the trace layer.

15. The semiconductor package structure of claim 13 , wherein the first portion of the trace layer is spaced apart from the second portion of the trace layer by a portion of the first substrate.

16. The semiconductor package structure of claim 10 , wherein a central axis of the first conductive pillar is misaligned with a central axis of the first conductive via in a vertical direction.

17. The semiconductor package structure of claim 10 , wherein the trace layer has a top surface and a bottom surface opposite to the top surface, the first conductive pillar is connected to the bottom surface of the trace layer, and the first surface of the first substrate is aligned with the top surface of the trace layer.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl
• Essig Kay Stefan

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title