Chip having memory

Patent metadata

Field	Value
Publication number	US-11880678-B2
Application number	US-202017118000-A
Country	US
Kind code	B2
Filing date	Dec 10, 2020
Priority date	Dec 11, 2019
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

A chip includes a power pin, a ground pin, a plurality of input/output (I/O) pins, a readable/writable memory, a switching circuit, and a control circuit. The I/O pins include a plurality of mapping pins and a control pin. The readable/writable memory includes a clock port, a plurality of I/O ports, and an enable port. The control circuit selectively activates or does not activate the switching circuit according to the control pin. When the switching circuit is activated, the switching circuit electrically couples the clock port, the I/O ports, and the enable port to the mapping pins respectively.

First claim

What is claimed is:

1. A chip, comprising:
a processing circuit;
a power pin;
a ground pin;
a plurality of input/output (I/O) pins including a control pin;
a readable/writable memory including a plurality of ports;
a switching circuit configured to electrically couple the ports to the I/O pins when activated; and
a control circuit configured to selectively activate or not activate the switching circuit according to the control pin, wherein when the switching circuit is not activated, the ports are electrically coupled to the processing circuit or the control circuit through the switching circuit, wherein the plurality of I/O pins further include a plurality of mapping pins, and when the switching circuit is activated, the ports are electrically coupled to the mapping pins respectively through the switching circuit.

2. The chip according to claim 1 , when the switching circuit is not activated, the mapping pins and the ports are electrically coupled to the processing circuit through the switching circuit.

3. The chip according to claim 1 , wherein the plurality of ports including a clock port, a plurality of I/O ports, and an enable port, and the switching circuit electrically couple the clock port, the I/O ports, and the enable port to the mapping pins respectively when activated.

4. The chip according to claim 3 , wherein when the switching circuit is not activated, the mapping pins, the clock port, the I/O ports, and the enable port are electrically coupled to the processing circuit through the switching circuit.

5. The chip according to claim 4 , wherein the processing circuit comprises a master controller, and when the switching circuit is not activated, the clock port, the I/O ports, and the enable port are electrically coupled to the master controller through the switching circuit.

6. The chip according to claim 3 , wherein the control circuit is a master controller, the master controller, according to the control pin, activates the switching circuit to electrically couple the clock port, the I/O ports, and the enable port to the mapping ports respectively, and when the switching circuit is not activated, the clock port, the I/O ports, and the enable port are electrically coupled to the master controller respectively through the switching circuit, and the mapping pins are electrically coupled to the processing circuit through the switching circuit.

7. The chip according to claim 3 , wherein the control circuit is a logic circuit, the I/O pins comprise a plurality of control pins, and the logic circuit activates the switching circuit when a combination of the control pins is a preset value.

8. The chip according to claim 3 , wherein the control circuit comprises:
a driving circuit configured to activate the switching circuit when activated; and
a communication circuit electrically coupled to the control pin and configured to activate the driving circuit according to the control pin.

9. The chip according to claim 3 , wherein the readable/writable memory is a non-volatile memory.

10. The chip according to claim 1 , wherein the control circuit is a logic circuit, the I/O pins comprise a plurality of control pins, and the logic circuit activates the switching circuit when a combination of the control pins is a preset value.

11. The chip according to claim 1 , wherein the control circuit comprises:
a driving circuit configured to activate the switching circuit when activated; and
a communication circuit electrically coupled to the control pin and configured to activate the driving circuit according to the control pin.

12. The chip according to claim 1 , wherein the readable/writable memory is a non-volatile memory.

Assignees

• Realtek Semiconductor Corp

Inventors

• Lin Neng-Hsien
• Geng Wan-Pei
• Feng Yao
• Shen Chen

Classifications

• G06F8/654 Primary

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F15/7842 Primary

  on one IC chip (single chip microcontrollers) · CPC title

• G06F8/63

  Image based installation; Cloning; Build to order · CPC title

• G06F8/65

  Updates (security arrangements therefor G06F21/57) · CPC title