System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

Patent metadata

Field	Value
Publication number	US-10261894-B2
Application number	US-201715447328-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	May 29, 2014
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

First claim

What is claimed is:

1. An integrated circuit comprising:
at least one processor forming a central processing unit in the integrated circuit;
a memory controller coupled to a memory external to the integrated circuit;
a first component configured to remain powered while the processor and the memory controller are powered off, wherein the first component comprises:
a local interconnect,
a local memory coupled to the local interconnect,
a second processor coupled to the local interconnect and configured to execute instructions stored in the local memory and process data stored in the local memory,
a reconfiguration circuit coupled to the local interconnect and configured to reconfigure the memory controller while the second processor remains powered down, and
a local power manager circuit configured to manage power up and power down of components within the first component including the local interconnect, the second processor, and the reconfiguration circuit; and

a communication fabric coupled to the processor, the local interconnect in the first component, and the memory controller, wherein:
the communication fabric includes a first section coupling the first component to the memory controller and a second section coupling the processor to the memory controller, wherein at least a portion of the second section is separate from the first section;
the first component is configured to cause the memory controller and the first section to power up while the portion of the second section remains powered down; and
the first component is configured to communicate with the memory controller while the portion of the second section and the processor remain powered down.

2. The integrated circuit as recited in claim 1 , wherein the first component is configured to store the configuration data for the memory controller, and wherein the reconfiguration circuit is configured to restore the configuration data over the local interconnect and the first section subsequent to powering up.

3. The integrated circuit as recited in claim 2 , wherein the configuration data represents a programmed configuration of the memory controller at a time that the memory controller was powered down.

4. The integrated circuit as recited in claim 3 , wherein the processor is configured to program the memory controller responsive to executing a plurality of instructions, and wherein the processor is further configured to write the configuration data to the first component responsive to executing the plurality of instructions prior to the processor being powered down.

5. The integrated circuit as recited in claim 2 , wherein the configuration data is predetermined data that is not dependent on the configuration of the memory controller at a time that the memory controller was powered down.

6. The integrated circuit as recited in claim 2 further comprising a plurality of components, wherein the first component is further configured to store configuration data representing the programmed configuration of each of the plurality of components at a time that the plurality of components were powered down.

7. The integrated circuit as recited in claim 6 , wherein the reconfiguration circuit is configured to program each of the plurality of components with the stored configuration data responsive to each of the plurality of components powering up.

8. The integrated circuit as recited in claim 1 , wherein the memory is placed in self-refresh mode prior to powering down the memory controller, and wherein the memory is removed from self-refresh mode in response to powering up the memory controller.

9. The integrated circuit as recited in claim 1 , wherein the communication fabric comprises a hierarchy of communication links and circuitry interfacing between levels of the hierarchy, wherein the first section includes a communication link at one or more levels in the hierarchy and the circuitry between the one or more levels.

10. The integrated circuit as recited in claim 9 , wherein at least one of the communication links is a point to point link.

11. A system comprising:
a memory; and
a system on a chip (SOC) coupled to the memory, the SOC including:
at least one processor forming a central processing unit in the SOC;
a memory controller configured to communicate with the memory during use;

a first component configured to remain powered while the processor and the memory controller are powered off, wherein the first component comprises:
a local interconnect,
a local memory coupled to the local interconnect,
a second processor coupled to the local interconnect and configured to execute instructions stored in the local memory and process data stored in the local memory,
a reconfiguration circuit coupled to the local interconnect and configured to reconfigure the memory controller while the second processor remains powered down, and
a local power manager circuit configured to manage power up and power down of components within the first component including the local interconnect, the second processor, and the reconfiguration circuit; and

a communication fabric coupled to the processor, the local interconnect in the first component, and the memory controller, wherein:
the communication fabric includes a first section coupling the first component to the memory controller and a second section coupling the processor to the memory controller, wherein at least a portion of the second section is separate from the first section;
the first component is configured to cause the memory controller and the first section to power up while the portion of the second section remains powered down; and
the first component is configured to communicate with the memory controller while the portion of the second section and the processor remain powered down.

12. The system as recited in claim 11 , wherein the first component is configured to store the configuration data for the memory controller, and wherein the reconfiguration circuit is configured to restore the configuration data over the local interconnect and the first section subsequent to powering up.

13. The system as recited in claim 12 , wherein the configuration data represents a programmed configuration of the memory controller at a time that the memory controller was powered down.

14. The system as recited in claim 13 , wherein the processor is configured to program the memory controller responsive to executing a plurality of instructions, and wherein the processor is further configured to write the configuration data to the first component responsive to executing the plurality of instructions prior to the processor being powered down.

15. The system as recited in claim 12 , wherein the configuration data is predetermined data that is not dependent on the configuration of the memory controller at a time that the memory controller was powered down.

16. The system as recited in claim 12 , wherein the SOC further comprises a plurality of components, wherein the first component is further configured to store configuration data representing the programmed configuration of each of the plurality of components at a time that the plurality of components were powered down.

17. The system as recited in claim 16 , wherein the first component is configured to program each of the plurality of components with the stored configuration data responsive to each of the plurality of components powering up.

18. The system as recited in claim 11 , wherein the memory is placed in self-refresh mode prior to powering down the memory controller, and wherein the memory

Assignees

• Apple Inc

Inventors

• Tripathi Brijesh
• Keil Shane J
• Gulati Manu
• Cho Jung Wook
• Machnicki Erik P
• Herbeck Gilbert H
• Millet Timothy J
• De Cesare Joshua P
• Dalal Anand

Classifications

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title