Efficient signaling scheme for high-speed ultra short reach interfaces

Patent metadata

Field	Value
Publication number	US-11880321-B2
Application number	US-202117521612-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Mar 28, 2016
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.

First claim

I claim:

1. A multi-chip module (MCM), comprising:
a substrate;
a first integrated circuit disposed on the substrate, the first integrated circuit including a first data input and output (I/O) port, the first data I/O port including i) a transmitter circuit configured to transmit first data, and ii) a receiver circuit configured to receive second data concurrently with transmission of the first data by the transmitter circuit;
a second integrated circuit disposed on the substrate and packaged with the first integrated circuit as part of a chip package, the second integrated circuit including a second data I/O port; and
a first channel comprising a circuit trace electrically coupling the first data I/O port and the second data I/O port, the first channel configured to concurrently and bidirectionally transfer the first data and the second data between the first integrated circuit and the second integrated circuit,
wherein the receiver circuit comprises echo interference cancellation circuitry, the echo interference cancellation circuitry configured to cancel echo interference associated with transmitting the first data over the first channel while concurrently receiving the second data over the first channel.

2. The MCM of claim 1 , wherein the first integrated circuit comprises a first timing signal I/O port, and the second integrated circuit comprises a second timing signal I/O port, the MCM further comprising:
a second channel comprising a second circuit trace electrically coupling the first timing signal I/O port and the second timing signal I/O port, the second channel configured to transfer a timing signal for synchronized transmission and receipt of the first data transmitted via the first channel.

3. The MCM of claim 2 , wherein:
the first integrated circuit generates the timing signal as a clock signal; and
the second integrated circuit operates in accordance with a second timing signal derived from the clock signal.

4. The MCM of claim 1 , wherein the echo interference cancellation circuitry is configured to cancel near-end echo interference arising from the transmission of the first data.

5. The MCM of claim 1 , wherein:
the first integrated circuit comprises a serializer-deserializer core; and
the second integrated circuit is configured as a network switch.

6. The MCM of claim 1 , wherein the first channel has a trace length of less than one inch.

7. The MCM of claim 6 , wherein the first channel has an effective electrical delay that, for propagation of a signal from the transmitter circuit of the first data I/O port to a second receiver circuit of the second data I/O port, is an integer multiple of half a symbol period of the signal.

8. The MCM of claim 1 , wherein the first data I/O port includes a termination impedance that is greater than 50 ohms.

9. A method of operating a multi-chip module (MCM), the MCM including a substrate, a first integrated circuit, and a second integrated circuit, the first integrated circuit and the second integrated circuit being disposed on the substrate, and a first signaling channel comprising a circuit trace electrically coupling the first integrated circuit and the second integrated circuit, the method comprising:
transmitting first data from the first integrated circuit to the second integrated circuit via the first signaling channel in a first direction;
while concurrently transmitting the first data in the first direction, receiving at the first integrated circuit second data transmitted from the second integrated circuit via the first signaling channel in a second direction opposite to the first direction; and
preventing echo interference associated with concurrently transmitting the first data from being output from a receiver of the first integrated circuit by canceling the echo interference at the receiver or prior to the echo interference being received at the receiver.

10. The method of claim 9 , wherein the transmitting of the first data comprises transmitting the first data from the first integrated circuit to the second integrated circuit via the first signaling channel in the first direction.

11. The method of claim 10 , further comprising transmitting a timing signal via a second signaling channel for synchronized transmission and receipt of the first data transmitted via the first signaling channel, wherein:
the MCM comprises the second signaling channel; and
the second signaling channel comprises a circuit trace electrically coupling the first integrated circuit and the second integrated circuit.

12. The method according to claim 11 , further comprising:
generating the timing signal at the first integrated circuit as a dock signal;
receiving the clock signal at the second integrated circuit; and
creating a second timing signal at the second integrated circuit that is derived from the clock signal.

13. The method according to claim 11 , wherein the canceling of echo interference associated with concurrently transmitting the first data comprises canceling near-end echo interference associated with concurrently transmitting the first data.

14. The method according to claim 12 , further comprising:
terminating the first integrated circuit with a first termination impedance that is greater than 50 ohms; and
terminating the second integrated circuit with a second termination impedance that is greater than 50 ohms.

15. The MCM of claim 1 , wherein the echo interference cancellation circuitry comprises a first impedance connected in series between a first output of the transmitter circuit and a first input of the receiver circuit.

16. The MCM of claim 15 , wherein the receiver circuit is configured to i) receive a first signal comprising the first data and the second data, and ii) receive a second signal comprising a complement of the first data, and to cancel the first data based on the complement of the first data to provide the second data.

17. The MCM of claim 15 , further comprising a second impedance connected in series with the first impedance between the first output of the transmitter circuit and the first input of the receiver circuit.

18. The MCM of claim 15 , wherein the transmitter circuit comprises a second output separate from the first output and configured to transmit the first data over the first channel.

19. The MCM of claim 15 , wherein the echo interference cancellation circuitry comprises a voltage divider comprising the first impedance and a second impedance, the second impedance is connected in series with the first impedance and a reference terminal.

20. The MCM of claim 19 , further comprising a gain stage connected in series with the first impedance between the first output of the transmitter circuit and the first input of the receiver circuit.

21. The MCM of claim 19 , wherein the second impedance is greater than the first impedance.

22. The MCM of claim 19 , wherein the echo interference cancellation circuitry is absent an impedance connected between the first impedance and a reference terminal.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Farjadrad Ramin

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• G06F13/36 Primary

  for access to common bus or bus system · CPC title

• H04L7/0091

  Transmitter details · CPC title

• H04L25/20

  Repeater circuits; Relay circuits · CPC title