Enabling efficient guest access to peripheral component interconnect express (PCIe) configuration space

Patent metadata

Field	Value
Publication number	US-11880301-B2
Application number	US-202218069851-A
Country	US
Kind code	B2
Filing date	Dec 21, 2022
Priority date	Jan 6, 2021
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.

First claim

What is claimed is:

1. A method comprising:
for each PCIe (Peripheral Component Interconnect Express) device function that is present in a virtual machine (VM) running on a host system:
reserving, by a hypervisor of the host system, a host physical memory page for the PCIe device function in a host physical memory of the host system; and
creating, in second-level page tables of the hypervisor, a mapping between the host physical memory page and a guest physical memory page of the VM that is addressed by a ECAM (Enhanced Configuration Access Mechanism) address of the PCIe device function,

wherein the created mapping specifies that the host physical memory page is writable, and
wherein the created mapping causes a guest operating system (OS) of the VM to directly retrieve contents of the host physical memory page upon accessing the ECAM address of the PCIe device function, without trapping into the hypervisor.

2. The method of claim 1 further comprising:
assigning one or more hardware resources of the host system to the PCIe device function; and
populating the host physical memory page with PCIe configuration space information for the PCIe device function.

3. The method of claim 2 wherein the PCIe configuration space information includes one or more PCIe EA (Enhanced Allocation) entries identifying the one or more hardware resources.

4. The method of claim 3 wherein each EA entry further includes an indicator indicating a BAR (base address register) of the PCIe device function.

5. The method of claim 2 wherein the one or more hardware resources include a memory address range in the host physical memory that is reserved for use by the PCIe device function.

6. The method of claim 1 further comprising:
marking a PCIe command register for the PCIe device function within the host physical memory page as being enabled.

7. The method of claim 1 further comprising:
modifying the created mapping to set the host physical memory page as read-only.

8. A non-transitory computer readable storage medium having stored thereon program code executable by a hypervisor of a host system, the program code causing the hypervisor to execute a method comprising, for each PCIe (Peripheral Component Interconnect Express) device function that is present in a virtual machine (VM) running on the host system:
reserving a host physical memory page for the PCIe device function in a host physical memory of the host system; and
creating, in second-level page tables of the hypervisor, a mapping between the host physical memory page and a guest physical memory page of the VM that is addressed by a ECAM (Enhanced Configuration Access Mechanism) address of the PCIe device function,
wherein the created mapping specifies that the host physical memory page is writable and
wherein the created mapping causes a guest operating system (OS) of the VM to directly retrieve contents of the host physical memory page upon accessing the ECAM address of the PCIe device function, without trapping into the hypervisor.

9. The non-transitory computer readable storage medium of claim 8 wherein the method further comprises:
assigning one or more hardware resources of the host system to the PCIe device function; and
populating the host physical memory page with PCIe configuration space information for the PCIe device function.

10. The non-transitory computer readable storage medium of claim 9 wherein the PCIe configuration space information includes one or more PCIe EA (Enhanced Allocation) entries identifying the one or more hardware resources.

11. The non-transitory computer readable storage medium of claim 10 wherein each EA entry further includes an indicator indicating a BAR (base address register) of the PCIe device function.

12. The non-transitory computer readable storage medium of claim 9 wherein the one or more hardware resources include a memory address range in the host physical memory that is reserved for use by the PCIe device function.

13. The non-transitory computer readable storage medium of claim 8 wherein the method further comprises:
marking a PCIe command register for the PCIe device function within the host physical memory page as being enabled.

14. The non-transitory computer readable storage medium of claim 8 wherein the method further comprises:
modifying the created mapping to set the host physical memory page as read-only.

15. A host system comprising:
a host physical memory;
a processor; and
a non-transitory computer readable medium having stored thereon program code for a hypervisor that, when executed by the processor, causes the hypervisor to:
reserve a host physical memory page for the PCIe device function in the host physical memory of the host system; and
create, in second-level page tables of the hypervisor, a mapping between the host physical memory page and a guest physical memory page of the VM that is addressed by a ECAM (Enhanced Configuration Access Mechanism) address of the PCIe device function,

wherein the created mapping specifies that the host physical memory page is writable and
wherein the created mapping causes a guest operating system (OS) of the VM to directly retrieve contents of the host physical memory page upon accessing the ECAM address of the PCIe device function, without trapping into the hypervisor.

16. The host system of claim 15 wherein the program code further causes the hypervisor to:
assign one or more hardware resources of the host system to the PCIe device function; and
populate the host physical memory page with PCIe configuration space information for the PCIe device function.

17. The host system of claim 16 wherein the PCIe configuration space information includes one or more PCIe EA (Enhanced Allocation) entries identifying the one or more hardware resources.

18. The host system of claim 17 wherein each EA entry further includes an indicator indicating a BAR (base address register) of the PCIe device function.

19. The host system of claim 16 wherein the one or more hardware resources include a memory address range in the host physical memory that is reserved for use by the PCIe device function.

20. The host system of claim 15 wherein the program code further causes the hypervisor to:
mark a PCIe command register for the PCIe device function within the host physical memory page as being enabled.

21. The host system of claim 15 wherein the program code further causes the hypervisor to:
modify the created mapping to set the host physical memory page as read-only.

Assignees

• VMware LLC

Inventors

• Warkentin Andrei
• Fainkichen Alexander
• Li Ye
• Duchesne Regis
• Laplace Cyprien
• Hiriyuru Shruthi
• Kotian Sunil

Classifications

• G06F12/0646 Primary

  Configuration or reconfiguration · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title