Page fault-based fast memory-mapped I/O for virtual machines

Patent metadata

Field	Value
Publication number	US-9846610-B2
Application number	US-201615018043-A
Country	US
Kind code	B2
Filing date	Feb 8, 2016
Priority date	Feb 8, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Implementations provide for page fault-based fast memory-mapped I/O for virtual machines. A method of the disclosure includes detecting, by a processing device executing a hypervisor on a host machine, a protection fault at the hypervisor, the protection fault caused by a guest of the hypervisor attempting to write to an address marked as valid and read-only in a host page table entry at the hypervisor, the address associated with memory-mapped input-output (MMIO) for a virtual device of the guest, referencing, by the processing device, a MMIO data structure of the hypervisor with the address that caused the protection fault, identifying, by the processing device, the virtual device and a MMIO-based instruction mapped to the address in the MMIO data structure at the hypervisor, and executing, by the processing device, the MMIO instruction at the hypervisor on behalf of the guest.

First claim

What is claimed is:

1. A method, comprising:
detecting, by a processing device executing a hypervisor on a host machine, a protection fault at the hypervisor, the protection fault caused by a guest of the hypervisor attempting to write to an address marked as valid and read-only in a host page table entry at the hypervisor, the address associated with memory-mapped input-output (MMIO) for a virtual device of the guest;
referencing a MMIO data structure of the hypervisor with the address corresponding to the protection fault;
identifying, by the processing device, the virtual device and a MMIO-based instruction mapped to the address in the MMIO data structure; and
executing, by the processing device, the MMIO-based instruction at the hypervisor on behalf of the guest.

2. The method of claim 1 , further comprising, during hypervisor initialization:
informing the guest, by the hypervisor, of the presence of the hypervisor;
requesting the guest, by the hypervisor, to provide one or more MMIO addresses with corresponding virtual device identification;
receiving from the guest, by the hypervisor, the one or more MMIO addresses with the corresponding virtual device identification;
determining, by the hypervisor, MMIO instructions that correspond with each of the received one or more MMIO addresses; and
storing, by the hypervisor, the one or more MMIO addresses with the corresponding virtual device identification and corresponding MMIO instructions in the MMIO data structure.

3. The method of claim 1 , further comprising marking, by the hypervisor, host page table entries corresponding to one or more MMIO addresses comprising the address as valid and read-only.

4. The method of claim 1 , wherein the MMIO data structure further comprises, for each entry corresponding to a MMIO address, at least one of the MMIO-based instruction, a virtual device identifier, data comprising one or more operands for the MMIO-based instruction, the type of the page fault detected, or a length of the data.

5. The method of claim 1 , further comprising:
detecting, by the hypervisor, a second page fault associated with a second non valid or reserved host page table entry; and
referencing, by the processing device, a second MMIO data structure of the hypervisor with the address that caused the second page fault.

6. The method of claim 1 , further comprising, responsive to the MMIO data structure having no match for at least one of (i) the address, (ii) the address and the data, or (iii) the address, the data, and the length, signaling an error to the guest and exiting to the hypervisor.

7. The method of claim 1 , wherein a translation of the address is stored in a translation lookaside buffer (TLB) when the guest accesses the address.

8. The method of claim 1 , wherein the guest performs a read operation on the address prior to the attempt to write to the address.

9. The method of claim 8 , wherein the read operation is performed after a determined number of write instructions are executed.

10. The method of claim 1 , wherein, when the virtual device is loaded in the guest, guest device drivers for the virtual device create writable mappings for pages corresponding to the memory space of the virtual device.

11. A computer system comprising:
a memory;
a host processing device, coupled to the memory, to execute a hypervisor from the memory, the hypervisor to virtualize resources of the computer system for one or more guests, wherein the host processing device to:
detect a protection fault at the hypervisor, the protection fault caused by a guest of the hypervisor attempting to write to an address marked as valid and read-only in a host page table entry at the hypervisor, the address associated with memory-mapped input-output (MMIO) for a virtual device of the guest;
reference a MMIO data structure of the hypervisor with the address corresponding to the protection fault;
identify the virtual device and a MMIO-based instruction mapped to the address in the MMIO data structure; and
execute the MMIO-based instruction at the hypervisor on behalf of the guest.

12. The computer system of claim 11 , wherein the processing device is further to cause the hypervisor to, during hypervisor initialization:
inform the guest of the presence of the hypervisor;
requesting the guest, by the hypervisor, to provide one or more MMIO addresses with corresponding virtual device identification;
receiving from the guest, by the hypervisor, the one or more MMIO addresses with the corresponding virtual device identification;
determining, by the hypervisor, MMIO instructions that correspond with each of the received one or more MMIO addresses; and
storing, by the hypervisor, the one or more MMIO addresses with the corresponding virtual device identification and corresponding MMIO instructions in the MMIO data structure.

13. The computer system of claim 11 , further comprising marking, by the hypervisor, host page table entries corresponding to one or more MMIO addresses comprising the address as valid and read-only.

14. The computer system of claim 11 , wherein the MMIO data structure further comprises, for each entry corresponding to a MMIO address, at least one of a MMIO-based instruction, a virtual device identifier, data comprising one or more operands for the MMIO-based instruction, or a length of the data.

15. The computer system of claim 11 , wherein a translation of the address is stored in a translation lookaside buffer (TLB) when the guest accesses the address.

16. The computer system of claim 11 , wherein the guest performs a read operation on the address prior to the attempt to write to the address.

17. A non-transitory computer-readable storage medium including instructions that, when accessed by a processing device, cause the processing device to:
request, by the processing device executing a hypervisor on a host machine, a guest of the hypervisor to provide one or more memory-mapped input-output (MMIO) addresses to the hypervisor, the MMIO addresses associated with memory space of a virtual device of the guest;
receive, from the guest, the one or more MMIO addresses at the hypervisor;
determine MMIO instructions that correspond with each of the received one or more MMIO addresses;
storing, by the processing device, the one or more MMIO addresses with corresponding virtual device identification and the corresponding MMIO instructions in a MMIO data structure of the hypervisor; and
marking, by the processing device, host page table entries corresponding to the one or more MMIO addresses as valid and read-only in a host page table entry at the hypervisor.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the processing device further to:
detect a protection fault at the hypervisor, the protection fault caused by the guest of the hypervisor attempting to write to an address of the MMIO addresses;
reference a MMIO data structure of the hypervisor with the address that caused the protection fault;
identify the virtual device and a MMIO-based instruction mapped to the address in the MMIO data structure at the hypervisor; and
execute the MMIO instruction at the hypervisor on behalf of the guest.

19. The non-transitory computer-readable storage medium of claim 17 , wherein a translation of the address is stored in a translation lookaside buffer (TLB) when the guest accesses the address.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the guest performs a read operation on the

Assignees

• Red Hat Israel Ltd

Inventors

• Tsirkin Michael

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/063

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title

• G06F11/0712

  in a virtual computing platform, e.g. logically partitioned systems · CPC title