Solid-state imaging device and electronic apparatus

US11877083B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11877083-B2
Application numberUS-201917419124-A
CountryUS
Kind codeB2
Filing dateDec 2, 2019
Priority dateDec 27, 2018
Publication dateJan 16, 2024
Grant dateJan 16, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A solid-state imaging device according to an embodiment of the present disclosure includes two or more pixels. The pixels each include a photoelectric converter, a charge holding section, and a transfer transistor. The charge holding section holds electric charge transferred from the photoelectric converter. The transfer transistor transfers electric charge from the photoelectric converter to the charge holding section. The pixels each further include a light blocking section that is disposed in a layer between the photoelectric converter and the charge holding section. The light blocking section has an opening which a vertical gate runs through. The pixels each further include a charge blocking section that blocks transfer of electric charge to the transfer transistor via a region between an edge, of the opening, closer to the charge holding section and the vertical gate.

First claim

Opening claim text (preview).

The invention claimed is: 1. A solid-state imaging device comprising: a light receiving surface; and two or more pixels that oppose the light receiving surface, wherein the pixels each include a photoelectric converter that performs photoelectric conversion on light entering via the light receiving surface, a charge holding section that holds electric charge transferred from the photoelectric converter, a transfer transistor that includes a vertical gate electrode reaching the photoelectric converter, and transfers electric charge from the photoelectric converter to the charge holding section, a light blocking section that is disposed in a layer between the photoelectric converter and the charge holding section and has an opening which the vertical gate runs through, the light blocking section blocking entry, into the charge holding section, of light entering via the light receiving surface at a part other than the opening, and a charge blocking section that blocks transfer of electric charge to the transfer transistor via a region between an edge, of the opening, closer to the charge holding section and the vertical gate. 2. The solid-state imaging device according to claim 1 , wherein the charge blocking section isolates the light blocking section and the vertical gate from each other. 3. The solid-state imaging device according to claim 1 , wherein the light blocking section and the vertical gate are both provided in contact with the charge blocking section. 4. The solid-state imaging device according to claim 2 , wherein the charge blocking section includes a single-layer film including a silicon oxide or a multilayer film including a silicon oxide film. 5. The solid-state imaging device according to claim 1 , wherein the vertical gate includes a wall that blocks entry, into the charge holding section, of light entering via the light receiving surface. 6. The solid-state imaging device according to claim 1 , further comprising a separator that is joined to each of the light blocking sections, the separator electrically and optically separating the pixels from each other. 7. The solid-state imaging device according to claim 6 , further comprising a semiconductor substrate that includes the light receiving surface and a formation surface for the transfer transistor, and on which each of the pixels is provided, wherein the separator is provided to extend from the light receiving surface to the formation surface. 8. An electronic apparatus comprising: a solid-state imaging device that outputs a pixel signal based on entering light; and a signal processing circuit that processes the pixel signal, wherein the solid-state imaging device includes a light receiving surface, and two or more pixels that oppose the light receiving surface, and the pixels each include a photoelectric converter that performs photoelectric conversion on light entering via the light receiving surface, a charge holding section that holds electric charge transferred from the photoelectric converter, a transfer transistor that includes a vertical gate electrode reaching the photoelectric converter, and transfers electric charge from the photoelectric converter to the charge holding section, a light blocking section that is disposed in a layer between the photoelectric converter and the charge holding section and has an opening which the vertical gate runs through, the light blocking section blocking entry, into the charge holding section, of light entering via the light receiving surface at a part other than the opening, and a charge blocking section that blocks transfer of electric charge to the transfer transistor via a region between an edge, of the opening, closer to the charge holding section and the vertical gate.

Assignees

Inventors

Classifications

  • the integrated elements comprising a transistor · CPC title

  • of CMOS image sensors · CPC title

  • Back-illuminated image sensors · CPC title

  • Pixel isolation structures · CPC title

  • Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels · CPC title

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Frequently asked questions

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What does patent US11877083B2 cover?
A solid-state imaging device according to an embodiment of the present disclosure includes two or more pixels. The pixels each include a photoelectric converter, a charge holding section, and a transfer transistor. The charge holding section holds electric charge transferred from the photoelectric converter. The transfer transistor transfers electric charge from the photoelectric converter to t…
Who is the assignee on this patent?
Sony Semiconductor Solutions Corp
What technology area does this patent fall under?
Primary CPC classification H10F39/8057. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 16 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).