Voltage delay compensation in a buck converter

US11876452B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11876452-B2
Application numberUS-202117477813-A
CountryUS
Kind codeB2
Filing dateSep 17, 2021
Priority dateDec 16, 2020
Publication dateJan 16, 2024
Grant dateJan 16, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A DC-DC converter including a switching buck regulator including a first power switch connected to a first power node, a second power switch connected to a second power node, a driver configured to drive the first and second power switches, an output filtering inductor connected to a node between the first and second power switches, and an output filtering capacitor connected to the output filtering inductor, a controller configured to compensate for an output signal of the switching buck regulator in a time domain using a reference voltage, and a feed forward circuit connected between the switching buck regulator and the controller, and including a first buffer, a second buffer, an RC filter, and an adder may be provided. Accordingly, the DC-DC converter can reduce a delay of a compensation circuit, improve transient response characteristics of the switching buck regulator, and further improve the performance of the DC-DC converter.

First claim

Opening claim text (preview).

What is claimed is: 1. A DC-DC converter, comprising: a switching buck regulator including a first power switch connected to a first power node for outputting a first power voltage, a second power switch connected to a second power node for outputting a second power voltage lower than the first power voltage, a driver configured to drive the first power switch and the second power switch, an output filtering inductor connected to a node between the first power switch and the second power switch, and an output filtering capacitor connected to the output filtering inductor; a controller configured to compensate for an output signal of the switching buck regulator in a time domain using a reference voltage; and a circuit connected between the switching buck regulator and the controller, the circuit including a first buffer, an RC filter, a second buffer, and an adder sequentially on a path, wherein an input terminal of the first buffer is connected to an output terminal of the switching buck regulator and the adder, and an output terminal of the first buffer is connected to the RC filter, and an input terminal of the second buffer is connected to the RC filter and the controller, and an output terminal of the second buffer is connected to the adder. 2. The DC-DC converter of claim 1 , further comprising: a voltage divider connected between the switching buck regulator and the circuit. 3. The DC-DC converter of claim 2 , wherein the voltage divider comprises a plurality of resistors, and the voltage divider is configured to determine a gain thereof based on the reference voltage. 4. The DC-DC converter of claim 1 , wherein the RC filter comprises: a compensation filtering capacitor connected to the output terminal of the first buffer and the input terminal of the second buffer; and a compensation filtering resistor connected to the compensation filtering capacitor and the input terminal of the second buffer. 5. The DC-DC converter of claim 4 , wherein the reference voltage is applied to the compensation filtering resistor. 6. The DC-DC converter of claim 1 , wherein the first buffer has a first gain, and the second buffer has a second gain. 7. The DC-DC converter of claim 1 , wherein the controller comprises a first voltage controlled oscillator, a second voltage controlled oscillator, a voltage controlled delay line, and a phase detector, wherein the phase detector is connected to the voltage controlled delay line connected to the first voltage controlled oscillator through a first path, and connected to the second voltage controlled oscillator through a second path separate from the first path. 8. The DC-DC converter of claim 7 , wherein the RC filter is connected to the voltage controlled delay line. 9. The DC-DC converter of claim 1 , wherein the controller comprises a phase detector connected to a first voltage controlled oscillator and a second voltage controlled oscillator, wherein the first voltage controlled oscillator is connected to the node between the first power switch and the second power switch. 10. A DC-DC converter, comprising: a switching buck regulator including a driver and configured to output a first output signal, the driver configured to drive a first power switch and a second power switch; a circuit connected to the switching buck regulator and including an adder, the circuit configured to generate a second output signal by performing a first operation on the first output signal, and output the first output signal and the second output signal using the adder; and a controller connected to the adder, the controller including a first voltage controlled oscillator configured to receive the first output signal and the second output signal from the adder, a second voltage controlled oscillator configured to receive a reference voltage, a voltage controlled delay line, and a phase detector, the phase detector connected to the voltage controlled delay line that is connected to the first voltage controlled oscillator through a first path and connected to the second voltage controlled oscillator through a second path separate from the first path, wherein the controller is configured to convert the first output signal and the second output signal into a time domain, perform a second operation on the converted first output signal and the converted second output signal, and perform a third operation to compensate for on a signal on which the second operation has been performed. 11. The DC-DC converter of claim 10 , wherein the first voltage controlled oscillator is configured to perform the second operation, the voltage controlled delay line is configured to perform the third operation. 12. The DC-DC converter of claim 10 , wherein the voltage controlled delay line is configured to generate a reset voltage, the second voltage controlled oscillator is configured to generate a set voltage, and the phase detector is configured to detect a phase difference between the set voltage and the reset voltage to generate a driving signal. 13. The DC-DC converter of claim 12 , wherein the driver is configured to output a switching signal for driving the first power switch and the second power switch based on the driving signal. 14. The DC-DC converter of claim 10 , wherein the first operation and the third operation are differential operations, and the second operation is an integral operation. 15. The DC-DC converter of claim 10 , wherein the DC-DC converter is configured to, output a first voltage before a driving signal is applied to the switching buck regulator, output a second voltage that is a target voltage after the driving signal is applied, and determine a time taken to output the second voltage after the driving signal is applied based on a gain of the voltage controlled delay line. 16. The DC-DC converter of claim 10 , wherein the circuit compensates for the first output signal based on disturbance for the first output signal. 17. The DC-DC converter of claim 10 , wherein the voltage controlled delay line is configured to reduce an overshoot when an output signal of the first voltage controlled oscillator abruptly changes. 18. A DC-DC converter, comprising: a switching buck regulator including a driver configured to output a switching signal for driving a first power switch and a second power switch based on a driving signal, the switching buck regulator configured to output a first output signal; a circuit connected to the switching buck regulator, the circuit including a first buffer, an RC filter, a second buffer, and an adder sequentially on a path, the circuit configured to output the first output signal together with a second output signal using the adder; and a controller including a voltage controlled delay line connected to a first voltage controlled oscillator and a phase detector connected to a second voltage controlled oscillator, the controller configured to convert the first output signal and the second output signal into a time domain, and generate the driving signal based on at least one of the converted first output signal or the converted second output signal. 19. The DC-DC converter of claim 18 , further comprising: a plurality of regulators corresponding to the switching buck regulator, wherein the controller is configured to generate a plurality of driving signals, which include the driving signal, corresponding to the plurality of regulators, and a plurality of drivers included in the plurality of regulators are configured to output a plurality of switchin

Assignees

Inventors

Classifications

  • H02M3/158Primary

    including plural semiconductor devices as final control devices for a single load · CPC title

  • Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters · CPC title

  • using active elements · CPC title

  • H02M3/1584Primary

    with a plurality of power processing stages connected in parallel · CPC title

  • H02M3/156Primary

    with automatic control of output voltage or current, e.g. switching regulators · CPC title

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What does patent US11876452B2 cover?
A DC-DC converter including a switching buck regulator including a first power switch connected to a first power node, a second power switch connected to a second power node, a driver configured to drive the first and second power switches, an output filtering inductor connected to a node between the first and second power switches, and an output filtering capacitor connected to the output filt…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H02M3/158. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 16 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).